EE 105 Spring 1997Lecture 13

CMOS Dynamic Logic

■

Static NOR gate

Idea: n-channel and p-channel devices separately perform the same logic function.

replace p-channels with a resistor -->

replace n-channels with a resistor -->

... two functions are identical by DeMorgan’s Theorem

■

Let n-channels perform the logic and get rid of the pull-up devices (or vice versa)

VDD

BA

A

B

Q

M4

M3

M1 M2 CL

Q A B+=

Q AB=

EE 105 Spring 1997Lecture 13

n-Channel CMOS Dynamic Logic

■

clock signal

φ

(

t

) charges up load capacitance through

M

P

(

P = precharge)

when it transitions from high to low;

M

E

(

E

= evaluate) is cutoff and prevents any discharge path of

C

L

through logic function transistors.

■

clock signal goes high -->

M

P

is cutoff,

M

E

conducts -->

C

L

discharges if one of the logic transistors has a high input.

■

Payoffs:

1. large fan-in NOR gates without huge p-channel load devices (also, avoids backgate effect on loads)

2. tends to be fast due to smaller load capacitances

■

Drawback:

1. clock is essential to refresh logic level stored on

C

L

, which complicates the design

MA B

φ

φ

ME

MP

VOUT

VDD

LogicFunction

CL

(a)

t

φ

VDD

(b)

evaluateevaluateprecharge

0

C

+

−

EE 105 Spring 1997Lecture 13

n-Channel Dynamic Logic Propagation Delays

■

Consider “

t

PLH

” to be the time required to pre-charge the output node

■

Charging current

M A B

φ = 0MP

VOUT (t = 0) = 0 V

VDDPrecharge Circuit (tPLH)

ME (cutoff)φ = 0

CL

IDp–k p

2----- VDD VTp+( )2

=

EE 105 Spring 1997Lecture 13

n-Channel Dynamic Logic Propagation Delays

■

Consider

“t

PHL

” to be the

worst-case

time to evaluate the logical function afterclock goes high.

■

Discharging current: assume (

W/L

)

E

= (

W/L

)

A

= ... (

W/L

)

M

and note that the transistors are in series -->effective value is

k

n

/ 2

0 V0 V

φ = 5 V MP (cutoff)VOUT (t = 0) = 0 V

VDD

Evaluate Circuit (tPHL)

ME φ = 5 V

CL

5 V

(only one input high)

IDnµnCox

kn

4-----

VDD VTn–( )2=

EE 105 Spring 1997Lecture 13

Boolean Functions in Dynamic Logic

■ Examples:

■ (a) n-channel dynamic logic

■ (b) p-channel dynamic logic

The output is “pre-discharged” to zero by MP and is only charged if there is a path through the logic transistors when the clock goes low and ME conducts.

VDD VDD

A

(a) (b)

AB

B

C

C D

Q

Q

MPME

MP MEφ

φ

φ

φ

Q A B+( )C=

Q AB C D+ +=

EE 105 Spring 1997Lecture 13

CMOS Transmission Gates

■ Need: “gate” signals by having a series switch that can be shorted or open-circuited.

■ Why n-channel and p-channel in parallel? Only one device (say, n-channel): can’t pass an input voltage > VDD - VTn, since device will enter the cutoff region

.

OUT

C

C

IN

(a) (b)

IN

C

OUT

C

5 V 0 V

G

D D

G

5 V − VTn 0 V − VTp

(a) charge-up (b) discharge

B0 V

B5 V

S S

5 V 0 V

EE 105 Spring 1997Lecture 13

Pass Transistor Logic

■ Advantages: reduced transistor count and higher speed compared with static CMOS

■ Disadvantage: reduced noise margins

SwitchingNetwork

A

B

B

B

(a)

(c)

OUT

A

B

B

B

(b)

OUT

EE 105 Spring 1997Lecture 13

The pn Junction under Forward Bias

■ VD > 0 --> what happens?

Many assumptions: from Chapter 6 (current not too big) -->resistive potential drops in bulk p & n regions can be neglectedin KVL and φj = φB - VD

φB = thermal equilibrium barrier height = φn - φp

��

���

���

��

�������

p

n

xn

− xp

depletion region

metal contact ton side

metal contactto p side

−xpo

−

+

xno

xn−xp0.1

0.2

0.3

0.4

− 0.4

− 0.3

− 0.2

− 0.1

φ(x)

φo(x)

x

(a)

(b)

x

− Wp

Wn

−Wp Wn

Vd = 0.7 V

−+

+

−

VD = 0.7 V

φj = 0.2 V

φB = 0.9 V

+−

EE 105 Spring 1997Lecture 13

Physical Reasoning

■ thermal equilibrium --> balance between drift and diffusion:

J = Jdrift + Jdiff = 0 for holes and electrons

■ forward bias upsets balance

− xpo xnox

(b)

− Wp Wn

− xpo xnox− Wp Wn

−xp xn

(a)

−xpo xnox− Wp Wn

−xp xn

Eo(x)

E(x)

po(x)

p(x)

(c)

−xp xn

Jpo

diff

Jpo

drift

Jp

diff

Jp

drift

Jpo = 0

Jp > 0

Na

linear scale

EE 105 Spring 1997Lecture 13

Modelling Forward-Bias Diode Currents

■ Step 1: find how minority carrier concentrations at the edges of depletion region change with forward bias VD

■ Step 2: what happens to the minority carrier concentration at the ohmic contacts under forward bias? Answer: no change from equilibrium.

■ Step 3: find the minority carrier concentrations np(x) in the p region and pn(x) in the n region.

■ Step 4: find the minority carrier diffusion currents.

■ Step 5: find the total current J.

EE 105 Spring 1997Lecture 13

Carrier Concentrations in Thermal Equilibriumat the pn Junction

■ For the junction in thermal equilibrium,

, where

If we identify pno = ni2 / Nd and npo = ni

2 / Na, we can reexpress this basic result in two ways --

.

■ Solving for the equilibrium minority carrier concentrations in terms of the built-in potential,

.

This result is very important, since it relates the minority carrier concentration on one side of the junction to the majority carrier concentration on the other side of the junction ... !

φBkTq

------lnNaNd

ni2

--------------( )=

φB VthlnNd

npo---------( )= and φB Vthln

Na

pno---------( )=

pno NaeφB Vth( )⁄–

= and npo NdeφB Vth( )⁄–

=

EE 105 Spring 1997Lecture 13

Law of the Junction

■ What happens under an applied bias?

assume that the new potential barrier φj = φB - VD can substituted for the thermal equilibrium barrier to find the new minority carrier concentrations at the depletion region edges -xp (p-side) and xn (n-side)

and

.

These results can be re-expressed in a simpler form, by expanding the exponentials:

■ These two equations are known as the Law of the Junction.

Note that the minority carrier concentration is an exponential function of the applied bias on the junction.

np xp–( ) Ndeφj Vth⁄–

NdeφB VD–( ) Vth⁄–

= =

pn xn( ) Naeφj Vth⁄–

NaeφB VD–( ) Vth⁄–

= =

np xp–( ) NdeφB Vth⁄–

eVD Vth⁄

npoeVD Vth⁄

==

pn xn( ) NaeφB Vth⁄–

eVD Vth⁄

pnoeVD Vth⁄

==