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A Novel 2.4GHz LNA with Digital Gain Control

using 0.18um CMOSKuo-Hua Cheng

1. Dept. of Communication engineering,

National Chiao Tung University,

Hsin Chu, Taiwan

2. Dept. of Computer and Communication,

SHU-TE University, Kaohsiung County, Taiwan

Email: khcheng1101@yahoo.com.tw

Christina F. JouDept. of Communication engineering,

National Chiao Tung University,

Hsin Chu, Taiwan

Email: christ@cc.nctu.edu.tw

AbstractThis paper presents a novel gain control methodfor 2.4 GHz LNA applications. In this design, a digital mode

gain control concept was implemented. This Chip can accept

an appropriate control bit that come from base band toachieve power saving. With digital mode gain control to

achieve low noise and high 1dB compression point

simultaneously without increasing any circuit and power

consumption. Depend on receiving signal strength, there are

four gain modes can be selecting automatically. The compact

CMOS LNA is optimized for low-power-consuming ISM band

applications and is fabricated using commercial 0.18um

CMOS process. With current re-use technology, the power

consumption and linearity can be optimizing. The fully

integrated 2.4GHZ gain controllable LNA exhibits 15.2dB

maximum gain, 4.1dB minimum gain, respectively. Also, the

LNA has excellent noise performance at high gain mode;

1.55dB of noise figure is achieved in this work. The digital

modes gain controllable LNA produces a 1-dB compression

output power of -10 dBm. It consumes 2.5mA current from asupply voltage of 1.8V.

I. INTRODUCTION

Gain control mechanisms are used extensively in modern

communication systems. Through gain control mechanism,

circuits can achieve signal dynamic range extension, power

saving and good linearity. In recently year, portables RF

communication market is growth rapidly. Power

consumption is a key issue. The LNA is first circuit in any

RF receiver system that handles a high dynamic range RF

signals, such as -80dBm to -15dBm for Bluetooth. There

are tow problems at the front end of receiver. First is fadingeffect. Second is reflection from a moving object. Both

effects can saturate or degrade receiver performance. A

LNA with gain control circuit can solve these problems.

The proposed novel gain control LNA integrates linear

gain controllability with digital control mode. Through

appropriate digital bit programmable, the LNA gain can be

variable from 4 dB to 15.2dB. The control ability of per bit

is 2.8dB/bit. A LNA with over 10dB gain controllable rage

is suitable for RF receiver application.

II. GAIN CONTROL METHOD QUICK VIEW

There many gain control methods have been presented

before in literature [1-10]. The following are some gain

control techniques.

Technique 1: Load switching, its superiors are simple

structure and noise figure is not affected bythe gain modes. The drawbacks are potential

pose voltage problems and gain step very

sensitive to parasitic of load chain.

Technique 2: Current Splitting, power wastage is the most

important drawback and noise figure

performance will be serious degrade.

Technique 3: Extra gain control stage, it has good

performance in input and output isolation but

need more extra devices power consumption.

Technique 4: Bias control, the gain of LNA can be varied

with its bias voltage. Also, extra circuits that

convert control signal from base band is need.

The gain controlling scheme proposed here not onlyachieves good NF but also extent the P1dB in low gain

mode. The gain control is circuitry also is simple and dont

put any extra circuits or waste more power consumption.

III. LNA TOPOLOGY AND CIRCUIT DESIGN

The low noise amplifier is generally the first active stage

in RF receiver. Low noise figure, sufficient gain and higher

linearity are required. Also, input and output impedance

matching and power consumption are important, too. Noise

figure of LNA is key factor in receiver system, which

determined receiver system sensitivity. Equation (1) is the

total noise figure of a cascade multiple stages. In the

equation (1), the NF of first stage dominates the lowerbound of total system. Therefore, in order to achieve

sensitivity requirement of receiver, the LNA typically

requires a very low noise figure and sufficiently high gain

at desired frequency band to guarantee a low noise and

high sensitivity system.

n

n

GG

NF

GG

NF

G

NFNFNF

...

1......

11

121

2

1

21

++

+

+= (1)

The circuit diagram of the proposed gain control LNA is

shown in figure 1. The cascade topology with inductive

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degeneration is frequently preferred, which offer low noise,

high gain, good input/output impedance matching and

stability. The M1 has to be optimized for noise figure.

While the noise figure of LNA is depends on gm of M1

transistor size, which depend on the bias current and width

Figure 1. Low Noise Amplifier with gain control mechanism

of MOSFETs. The device scaling effects on the noise

parameters is derived by [11]. The four noise parameters

are as follows:

2

min ||1(1 cFT

+ (2)

2

0

m

d

g

gRn

(3)

2

0

||1( c

g

GgG

d

gsm

opt

(4)

0

1(d

mgsopt

g

gcCB (5)

The angular cutoff frequency Tis inverse proportional

to Leff. In (3) Rn is proportional to 1/ 2mg that meansshorter device improve Rn. Equation (2)-(5) imply that the

large device width and minimum device channel length

offers the best noise performance. To achieve better noise

figure and reasonable power dissipation, optimum width of

transistor M1 is given by [12]

8.02.16.0

)(

soxEFF

optRCL

IKW = . (6)

in which K(I) is a constant, depend on the biasing current

Id and M1. Under this condition the input impedance is

given by

LssC

LsLgsZin Tgs

+++1

)( (7)

At resonate condition (7) can be simplify

LsZin T (8)

The gain control mechanism is achieved by M2 transistor

that split into N sub-transistor for gain control. Depend on

receiving signal strength; base band providing control

mode of active or sleep. There are 4 bits in the proposed

LNA. The gain bias voltage is control voltage Vctrl0 ~

Vctrl3 and are varied from 0 to 1.8V. The gain control bit

has about 3.5dB gain step/per bit. The advantage of this

scheme over other gain control methods [1-10] is that the

LNA dont need extra control circuits, designer can easy to

program the desirable gain control step by appropriateto

split M2 into n-bit control transistor and a simple circuitrystructure for RF design.

IV. Simulation Result and Layout consideration

The LNA circuit simulation was using Mentor Graphic

Eldo-RF. Figure 2 shows the S21 curve of the LNA in

different gain control mode. It found that the gain of LNA,

S21, is centered at 2.4GHz with a high gain value of

15.2dB and low gain value of 4dB. The noise figure shown

in figure 3, it has minimum NF at high gain mode that

value is 1.5dB at 2.4GHz.

The 1 dB compression point P1dB is -8.5dBm at low

gain mode. Following the 9dB rule of thumb between P1db

and IIP3, which corresponding IIP3 is about -0.5dBm.When control bit is set at 1111, the LNA is working at

high gain mode. Also, set at 0001, the LNA is working in

low gain mode. Table I shows that the low gain mode

(0001) consumes 25% less power than high gain mode

(1111). The P1db has 5.4dB improved at low gain mode

and excellent noise figure at high gain mode.

As we known, the silicon substrate of the CMOS

technology is very noise. The conventional signal PADs

are easily including noise and extra substrate loss from the

parasitic resistance between metal plate and substrate.

Therefore, we use shielding PAD as shown in figure 4[13],

to shield the undesired effects cause by the noisy substrate.

Figure 5 shows the novel gain control LNA layout. To

achieve higher on-chip inductor Q-factor, the symmetric

structure type was adopted. The optimum M1 size is

245um. There are some layout skills to improve the LNA

noise performance. First, use multiple finger layout to

reduce distributed gate resistance and both side gate contact

that can lower Rg about 1/12 [14]. Second, increase

substrate contacts to reduce substrate resistance, Rb [15-

16]. To isolate the noise substrate, all RF signal paths

should be with metal shield.

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-15

-10

-5

0

5

10

15

20

1 2 3 4

Freq.(GHz)

dB

gain mode(1111)

gain mode(0111)

gain mode(0011)

gain mode(0001)

0

1

2

3

4

5

6

7

8

9

10

1 1.5 2 2.5 3 3.5 4

freq.(GHz)

dB

gain mode(1111)

gain mode(0111

gain mode(0011)gain mode (0001)

V. CONCLUSION

A novel gain control LNA operating in 2.4GHz using

standard 0.18um 1P6M CMOS technology was

demonstrated. A simple and flexible gain control

mechanism is adopted in LNA design. With appropriatebit

control, the gain can vary from 4.18dB to 15.2dB. Theexcellent noise figure performance, 1.5dB, is at high gain

mode. While a -8.5dB P1dB in low gain mode. The power

consumption for the mode of operation is 4.65mW at low

gain mode and 6.2mW at high gain mode.

Figure 2. S21 simulation result of LNA at 4 gain control mode

Figure 3. Noise figure simulation result of LNA at 4 gain control mode

Figure 4 Shielded signal PAD structure

Figure 5. LNA layout view

Table 1. 4 gain mode LNA specification simulation result

Mode S21(dB) S11(dB) NF(dB) P1db

(dBm)

Power

Consumption

1111 -18.8 15.2 1.5 -13.9 6.2mW

0111 -14.8 11.5 2.02 -12.76 5.8mW

0011 -13.1 8.09 2.87 -13 5.3mW

0001 -10.5 4.15 4.45 -13.9 4.65mW

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