A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit ...eeic7.sogang.ac.kr/paper...

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A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit Sharing Techniques Beom-Soo Park, Seung-Hak Ji, Min-Ho Choi, Kyung-Hoon Lee, Gil-Cho Ahn, and Seung-Hoon Lee Dept. of Electronic Engineering, Sogang University, Seoul, Korea : [email protected] AbstractThis work describes a 10b 100MS/s 0.18μm CMOS three-stage pipeline ADC. Two MDACs share an op-amp without MOS switches connected in series while removing a memory effect. Three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC with an active die area of 0.80mm 2 shows DNL and INL within 0.58LSB and 0.94LSB, respectively, and consumes 25.2mW at 1.8V and 100MS/s. Keywords-circuit sharing; low power; small size; ADC. I. INTRODUCTION The wireless local area network (WLAN) such as the IEEE 802.11n standard substitutes a conventional LAN and offers a potential of high throughputs to meet the requirements of various multimedia services. The IEEE 802.11n standard employs a multiple-input multiple-output (MIMO) technology with 4-channel antennas to obtain high throughputs and signal integrity. Such MIMO technology requires A/D converters (ADCs) with a 10b resolution and a signal bandwidth of 40MHz for transceiver blocks [1]. Of various well-known ADC architectures, the Nyquist-rate pipeline ADC has been employed as one of the best candidates to achieve a 10b resolution and a sampling rate of 100MS/s level with moderate power consumption and chip area. Especially, as the power-efficiency of ADCs becomes more important due to the increasing demand for system-on-a-chip implementation, various approaches have been invented. The ADC without using a sample-and-hold amplifier (SHA) saves a great amount of power dissipation and chip area [2]. Alternative approaches as observed in the ADC with a zero-crossing-based circuit (ZCBC) or the ADC using source followers eliminate residue amplifiers consuming most of the ADC power [3]-[4]. However, the SHA-free architecture suffers from the aperture error caused by the RC delay mismatches between the first multiplying digital-to-analog converter (MDAC) and the first flash ADC, which introduces significant sampling errors. The ZCBC has a finite delay issue due to the zero-crossing detector (ZCD) during residue amplification. The overshoot voltage caused by the ZCD limits the overall sampling rate and requires additional correction circuits to reduce the overshoot. Similarly, the ADC using source followers as a residue amplifier needs auxiliary digital calibration to remove the nonlinearity resulted from the parasitic components of MOS transistors. This work, on the other hand, proposes a pipeline ADC sharing as many circuits as possible to minimize power consumption and chip area with no calibration while obtaining a 10b resolution at 100MS/s. The proposed 10b ADC reduces the dissipated power and chip area of the first and second MDACs (MDAC1 and MDAC2) by sharing a residue amplifier consuming most of the ADC power. All three flash ADCs employ only one resistor ladder while the second and third flash ADCs share all pre- amps. The well-known interpolation technique employed in the flash ADCs halves the required number of pre-amps and reduces power consumption and chip area further. II. ADC ARCHITECTURE The proposed 10b 100MS/s three-stage pipeline ADC as shown in Fig. 1(a) consists of an input SHA, two 4b MDACs, three 4b flash ADCs, a digital correction logic (DCL) block, a timing circuit, and on-chip current and voltage (I/V) references with internal RC filters. (a) (b) Figure 1. Proposed 10b 100MS/s 0.18μm CMOS ADC: (a) overall ADC architecture and (b) two versions of the MDACs. 978-1-4244-5035-0/09/$26.00 ©2009 IEEE -329- ISOCC 2009

Transcript of A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit ...eeic7.sogang.ac.kr/paper...

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A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit Sharing Techniques

Beom-Soo Park, Seung-Hak Ji, Min-Ho Choi, Kyung-Hoon Lee, Gil-Cho Ahn, and Seung-Hoon Lee Dept. of Electronic Engineering, Sogang University, Seoul, Korea : [email protected]

Abstract—This work describes a 10b 100MS/s 0.18μm CMOS three-stage pipeline ADC. Two MDACs share an op-amp without MOS switches connected in series while removing a memory effect. Three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC with an active die area of 0.80mm2 shows DNL and INL within 0.58LSB and 0.94LSB, respectively, and consumes 25.2mW at 1.8V and 100MS/s.

Keywords-circuit sharing; low power; small size; ADC.

I. INTRODUCTION The wireless local area network (WLAN) such as the IEEE

802.11n standard substitutes a conventional LAN and offers a potential of high throughputs to meet the requirements of various multimedia services. The IEEE 802.11n standard employs a multiple-input multiple-output (MIMO) technology with 4-channel antennas to obtain high throughputs and signal integrity. Such MIMO technology requires A/D converters (ADCs) with a 10b resolution and a signal bandwidth of 40MHz for transceiver blocks [1].

Of various well-known ADC architectures, the Nyquist-rate pipeline ADC has been employed as one of the best candidates to achieve a 10b resolution and a sampling rate of 100MS/s level with moderate power consumption and chip area. Especially, as the power-efficiency of ADCs becomes more important due to the increasing demand for system-on-a-chip implementation, various approaches have been invented.

The ADC without using a sample-and-hold amplifier (SHA) saves a great amount of power dissipation and chip area [2]. Alternative approaches as observed in the ADC with a zero-crossing-based circuit (ZCBC) or the ADC using source followers eliminate residue amplifiers consuming most of the ADC power [3]-[4]. However, the SHA-free architecture suffers from the aperture error caused by the RC delay mismatches between the first multiplying digital-to-analog converter (MDAC) and the first flash ADC, which introduces significant sampling errors. The ZCBC has a finite delay issue due to the zero-crossing detector (ZCD) during residue amplification. The overshoot voltage caused by the ZCD limits the overall sampling rate and requires additional correction circuits to reduce the overshoot. Similarly, the ADC using source followers as a residue amplifier needs auxiliary digital calibration to remove the nonlinearity resulted from the

parasitic components of MOS transistors. This work, on the other hand, proposes a pipeline ADC sharing as many circuits as possible to minimize power consumption and chip area with no calibration while obtaining a 10b resolution at 100MS/s.

The proposed 10b ADC reduces the dissipated power and chip area of the first and second MDACs (MDAC1 and MDAC2) by sharing a residue amplifier consuming most of the ADC power. All three flash ADCs employ only one resistor ladder while the second and third flash ADCs share all pre-amps. The well-known interpolation technique employed in the flash ADCs halves the required number of pre-amps and reduces power consumption and chip area further.

II. ADC ARCHITECTURE The proposed 10b 100MS/s three-stage pipeline ADC as

shown in Fig. 1(a) consists of an input SHA, two 4b MDACs, three 4b flash ADCs, a digital correction logic (DCL) block, a timing circuit, and on-chip current and voltage (I/V) references with internal RC filters.

(a)

(b)

Figure 1. Proposed 10b 100MS/s 0.18μm CMOS ADC: (a) overall ADC architecture and (b) two versions of the MDACs.

978-1-4244-5035-0/09/$26.00 ©2009 IEEE -329- ISOCC 2009

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Two versions of the prototype ADC implement different types of circuit sharing techniques in the SHA, MDAC1, and MDAC2 while the remaining circuits are identical. In the Version1 ADC, the input SHA employs a gain-boosted folded-cascode amplifier while the MDAC1 and MDAC2 share the second amplifier of a two-stage op-amp as shown in Fig 2(b). On the other hand, the SHA in the Version2 ADC employs a conventional folded-cascode amplifier without gain-boosting circuits whereas the MDAC1 and MDAC2 share a single two-stage op-amp.

The shared output of the MDAC1 and MDAC2 is tied to the FLASH ADC2 (FLASH2) and FLASH ADC3 (FLASH3) simultaneously, and the shared pre-amps of the FLASH2 and FLASH3 reduce the shared output load of the MDAC1 and MDAC2 by 50%. All the three flash ADCs share a single resistor ladder for reference voltages and employ a kickback-reduced dynamic latch. The single resistor ladder provides the exactly same reference voltages for each flash ADC with a reduced chip area while the latch minimizes the kickback glitch generated at a transition point. The digital blocks such as the flash ADCs and DCL are designed to operate down to a 1.2V power supply to further reduce the dissipated power of the overall ADC.

III. CIRCUIT IMPLEMENTATION

A. SHA Based on Gain-boosting Technique The input SHA requires a high DC gain to handle input

signals without distortion. The SHA based on a conventional single-stage folded-cascode amplifier in the Version2 ADC achieves a DC gain of 60dB for 10b accuracy. On the other hand, as shown in Fig. 2, the SHA in the Version1 ADC employs extra gain-boosting circuits to the single-stage folded-cascode amplifier to increase a DC gain considering process variations and device non-idealities.

With this specific 0.18um CMOS technology, the output resistance of the folded-cascode architecture is determined by PMOS rather than NMOS cascode transistors at the output stage. Therefore, a gain-boosting technique is applied only to the PMOS cascode transistors to obtain a high enough DC gain for 10b with a small amount of added power consumption and chip area. A simple common-source amplifier with an active source-degeneration resistor is used for gain boosting, while the bias voltages for the gain-boosting circuit are shared with the main amplifier to reduce chip area and power consumption.

Figure 2. Gain-boosted amplifier in the SHA of the Version1 ADC.

However, a closely spaced pole and zero (doublet) due to the auxiliary amplifier may seriously degrade signal settling behavior [5]. As shown in Fig 2, a capacitor located at the output of each gain-boosting amplifier properly controls the doublet, and therefore enhances the operating performance of the amplifier. The SHA based on the proposed gain-boosted folded-cascode amplifier is simulated to have a DC gain of 72dB consuming 4.4mW which is 0.7mW more than the SHA with a conventional folded-cascode amplifier.

B. Op-amp Sharing Technique in MDACs Since op-amps are the most power-hungry analog circuit

elements in high-speed pipeline ADCs, various op-amp sharing techniques have been proposed to minimize the power consumption and chip area of the overall ADC. The motivation of the op-amp sharing technique is based on the fact that the op-amp operates only during a half of a full clock cycle in the switched-capacitor architecture. As a result, a single op-amp can be employed for residue amplification of two successive pipeline stages at different phases. However, some conventional op-amp sharing techniques have drawbacks as well as merits. The extra signal-forwarding switches in analog signal paths introduce a series resistance, which may degrade signal settling due to the increased parasitic capacitance and the offset voltage caused by charge injection and clock feed-through errors. Moreover, since the input summing nodes of op-amp are never reset, every sampled input is affected by a residual charge from the previously sampled input. The op-amp sharing techniques proposed in this work eliminate the parasitic effect due to extra series switches between the capacitor arrays and the shared op-amp, simultaneously with the memory effect coming from the non-reset input nodes of op-amp.

As shown in Fig. 3(a), the MDAC1 op-amp of the Version1 ADC consists of two amplifiers, A1 and AS, whereas the op-amp of the MDAC2 consists of two amplifiers, A2 and AS, respectively, with the shared amplifier of AS. On the other hand, the MDAC1 and MDAC2 of the Version2 ADC share a two-stage op-amp composed of AS1 and AS2, as shown in Fig. 3(b). During the Q1 clock phase, the capacitor arrays of the MDAC1 sample an SHA output, VIN1, while the op-amp of the MDAC2 amplifies a residue voltage reconstructed by the MDAC1 output and the digital code of the FLASH2. During the next Q2 clock phase, the capacitor arrays of the MDAC2 sample the output of the MDAC1 while the two-stage op-amp of the MDAC1 amplifies a residue voltage reconstructed by the SHA output and the digital output of the FLASH ADC1 (FLASH1).

The shared second amplifier, AS, of the Version1 ADC and the shared first amplifier, AS1, of the Version2 ADC are based on an op-amp reusing a bias current, as shown in Fig. 4 [6]. One input transistor pair connected to a fixed bias voltage operates as an active load for the other input transistor pair during residue amplification. Two input transistor pairs alternate their role sequentially from an input transistor to an active load depending on the employed clock phases without extra series MOS switches. As a result, both versions of the op-amp sharing technique eliminate the negative effect due to the switches between the capacitor arrays and the shared amplifier.

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(a)

(b)

Figure 3. Proposed op-amp sharing technique: (a) Version1 ADC and (b) Version2 ADC.

(a) (b)

Figure 4. Op-amp with bias current reuse: (a) AS of the Version1 ADC and (b) AS1 of theVersion2 ADC.

Since the input nodes of transistors operating as a load at the shared amplifier are reset alternately to a fixed bias voltage such as a signal ground, the memory effect also disappears.

C. Area and Power-efficient Circuit Sharing in flash ADCs The three 4b flash ADCs as shown in Fig. 5 employ a

variety of circuit sharing techniques to reduce chip area and power consumption. A single resistor ladder generating the required reference voltages is shared in all of the flash ADCs. The shared resistor ladder also removes the difference between reference voltages in each flash ADC and improves the overall ADC linearity. The FLASH2 and FLASH3 share the pre-amps based on a difference differential amplifier (DDA) circuit to reduce the power dissipation and the MDAC load by 50%. The shared DDA in Fig. 6 amplifies the output of the MDAC1 and MDAC2 at both of the Q1 and Q2 phases, continuously.

Figure 5. Circuit sharing schemes proposed in three 4b flash ADCs.

Figure 6. Shared DDA with a kickback-reduced dynamic latch.

A conventional interpolation technique reduces the required number of pre-amps in a half. However, the proposed shared pre-amp and interpolation techniques have a drawback that each shared pre-amp output needs to drive four latches instead of two as shown in Fig. 6. The resulting increased kickback noise can degrade the signal settling time of the SHA and MDACs, the accuracy of reference voltages, and the dynamic performance of the ADC [7]. The kickback-reduced dynamic latch proposed in Fig. 6 employs two NMOS pull-down switches located between input NMOS transistors and output NMOS transistors to minimize the output voltage variation causing the kickback noise. Moreover, the pre-amps in three flash ADCs and all of the on-chip digital circuits are designed to operate down to 1.2V to reduce power further.

IV. MEASUREMENT RESULTS The prototype ADC is fabricated in a 0.18μm CMOS and

occupies an active die area of 0.80mm2 as shown in Fig. 7. The total power consumption of the Version1 and Version 2 ADCs is 27.9mW and 25.2mW, respectively, at 1.8V and 100MS/s. Two versions of the ADC show a similar performance, while a slight degradation of dynamic performance occurs with a 1.2V digital supply. As illustrated in Fig. 8, the measured differential non-linearity (DNL) and integral non-linearity (INL) of the Version2 ADC are within 0.58LSB and 0.94LSB, respectively. At a maximum clock frequency of 100MS/s, the measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the Version2 ADC with a 4MHz, 1.2Vp-p input signal are 53.2dB and 68.3dB, respectively, as plotted in Fig. 9. The measured SNDR and SFDR with

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different sampling frequencies up to 100MS/s are illustrated in Fig. 10. Using a figure of merit defined as Power/(2ENOB×fs), the Version1 and Version2 ADCs achieve 0.82pJ/conv-step and 0.67pJ/conv-step. The SNDR and SFDR of the Version2 ADC are maintained above 51.5dB and 64.2dB, respectively, up to the Nyquist rate frequency of 50MHz input as illustrated in Fig. 11. The measured performance of the prototype ADC is summarized in Table I.

Figure 7. Chip photograph of the prototype ADC (1.08mm × 0.74mm).

Figure 8. Measured DNL and INL of the Version2 ADC.

Figure 9. Measured FFT spectrum of the Version2 ADC.

Figure 10. Measured SNDR and SFDR versus sampling frequency.

Figure 11. Measured SNDR and SFDR versus input frequency.

TABLE I. PERFORMANCE SUMMARY OF THE PROTOTYPE ADC

*VERSION1 : SHA with a gain-boosted folded-cascode amplifier MDACs based on the second amplifier sharing of a two-stage amplifier *VERSION2 : SHA with a conventional folded-cascode amplifier MDACs based on a single two-stage amplifier sharing

ACKNOWLEDGMENT This work was supported by Dongbu HiTek, System IC

2010 Project of Korea Ministry of Knowledge Economy, and the IDEC of KAIST, Korea.

REFERENCES [1] T. Paul and T. Ogunfunmi, “Wireless LAN comes of age: understanding

the IEEE 802.11n amendment,” IEEE Circuits and Systems Magazine, pp. 28-54, Jan. 2008.

[2] B. G. Lee and R. M. Tsang, “A 10-bit 50MS/s pipelined ADC with capacitor-sharing and variable-gm opamp,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 883-890, Mar. 2009.

[3] S. K. Shin et al, “A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 218-219.

[4] J. Hu, N. Dolev, and B. Murman, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1057-1066, Apr. 2009.

[5] K. Bult and G. Geelen "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990.

[6] S. T. Ryu, B. S. Song, and K. Bacrania, “A 10-bit 50-MS/s pipelined ADC with op amp current reuse,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 475-485, Mar. 2007.

[7] P. Figueiredo and J. C. Vital, “Kickback noise reduction technique for CMOS latched comparators,” IEEE Transactions on Circuit and Systems II, vol. 53, no. 7, pp. 541-545, Jul. 2006.

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