RBMicrocontroller HC12 1 Microcontrollers General 8 bits μControllers Example : 68HC912BC32...

RB Microcontroller HC12 1

Microcontrollers

General 8 bits μControllers

Example : 68HC912BC32

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General Architecture Memories Models Programmable Interfaces Access Types of Programmable Interfaces HC12 Architecture


General Architecture

A μC (microcontroller) is an integrated circuit with all the elements of a Computer System include on ONE chip: Processor(s) Memory (memories) Programmable Interfaces

Some μC adds the capability to extend external memories and Progr. Interfaces, they have external Add/Data/Ctrl busses.


General System Architecture

MicroprocessorMicroprocessor

MemoriesMemoriesDecoder

Decoder

Address Bus

Data Bus

ProgramDataStack

ProgramDataStack

Inputs

Outputs

Interfaces

Inputs

Outputs

Interfaces

Control Bus

A23..A0

D15..D0

D7..D0

Ax..A0

/P

R_/W


General System Architecture, μController



Decoder

Address Bus

Data Bus

ProgramDataStack

ProgramDataStack

Inputs

Outputs

Interfaces

Inputs

Outputs

Interfaces

Control Bus

A23..A0

D15..D0

D7..D0

Ax..A0

/P

R_/W


General System Architecture, μController + External bus



Decoder

Address Bus

Data Bus

ProgramDataStack

ProgramDataStack

Inputs

Outputs

Interfaces

Inputs

Outputs

Interfaces

Control Bus

A23..A0

D15..D0

D7..D0

Ax..A0

/P

R_/W


General Architecture

Some circuits does not provides memory, only the processor and some programmable interfaces they are generally named embedded processor.


Embedded controller 68331



Decoder

Address Bus

Data Bus

ProgramDataStack

ProgramDataStack

Inputs

Outputs

Interfaces

Inputs

Outputs

Interfaces

Control Bus

A23..A0

D15..D0

D7..D0

Ax..A0

/P

R_/W


Memories Models

μC can have von Neumann memory model, a unified memory scheme for Program /Data and stack memories

μC can have separate physical areas for program/data and stack, sometimes with different bus width (ex. PIC)


Programmable Interfaces Access

Depending on the processor family, the access to the programmable interface part is done : Memory Mapped I/O (ex. 68HC12) Through specialized instructions (ex. IN/OUT) Special area pages (ex. 8051 SFR space) Through specific Pointer/data registers couple

(ex. 8051 DPTR register)


Some Programmable Interfaces

Parallel ports Timer Analog to Digital Converter (ADC, ATD) Digital to Analog Converter (DAC) Pulse Width Modulation (PWM) Serial Interfaces:

UART (Universal Asynchronous Receiver/Transmitter) SPI (Synchronous Peripheral Interface) I2C CAN Ethernet …

…


Some Very known Families of 8 bits μC

8051 based μC (intel many manufacturer) AVR 68HC05, HC08, HC11, HC12 (Motorola Freescale)

PIC (Microchip) …


Models

In each of those families it exists a lot of different models : Size in memories (RAM, ROM, EPROM, Flash,…) Kind of programmable interfaces Power consumption (μW..W) Working frequencies (MHz..GHz) Type of packages (DIL, SOP, TSSOP, BGA, μBGA,.. ) Number of pins (6..hundred) …


Study case

For some practical examples and laboratories, we develop the 68HC12

The general concepts are similar


HC12 Architecture

Processor CPU12 32 Kbytes Flash EEPROM 1 Kbytes RAM 768 bytes EEPROM PORTAD A/D 8 channels 10

bits

PORTT Timer PORTS Serial SCI, SPI, 2 I/O PORTP 4 PWM, 4 I/O PORTCAN CANBUS, 5 I/O PORTA Address/Data PORTB Address/Data PORTE Control BDI Debug


Example, ManHC12 board

J10

PortP

J4

PortT PortE

PortAn PortS PortCAN

J3 J8

J7 J6 J5

PortB J2

68HC12 BC32

RS232

W4

J16

BDI

J20

PortA J1

Données

Adresse

Ctrl Mubus

Alim +5V

Vprog +12v

W3

MANHC12


ManHC12

J2

J1

Port P Port T Port E

Port SPort CAN Port An

Port B

Port A

RxD RS232

Enable 12VModB ModA

BDI

RS232

Reset

Vcc Gnd

EClk

Reset*

VFP

BGND

V12

PP7PP0

MUBUS


Debugging tools


Small experimentation

ATD PWM uP +

Programme

PortAn

PortP

Potentiomètre externe

External Potentiometer

μP+

Program

Final goal for the laboratory:Pot. ATD conversion PWM

Sampling Time generated by Timer and periodic Interrupts


CPU12, register's model

8 bits data registers: A & B A – B : 16 bits : D

16 bits pointers registers :IX et IY

Stack Pointer : SP Program Counter Register :

PC Flags CCR (Condition Code

register) : S X H I N Z V C


CPU12, modes

Modes: Special (Debug) Normal

Use of pins: μController (single chip) Expanded Mode, Ports used as Addr/Data/Ctrl

8 bits16 bits


CPU12, modes


CPU12, memory map

FlashE2PROM

Default map

RAM

E2PROM

Registers


HC12, Registers I/O

R.Beuchat Interruptions 27

HC12 Interrupts

General Mask: bit I Flags register I=0 Interrupts enabled (instruction CLI: Clear I) I=1 Interrupts disabled (instruction SEI: Set I)

Individual Interrupts masks One bit by interrupt source

Event

Clear IRQlocal (Write «1»)

IRQ Local

Enable Local Interrupt

IRQ uP

IRQ a

IRQ x

IRQ b

CCR Flags: I

IRQ …


CPU12, Interrupts, Vector table

For each interrupt source : a specific entry in the vector table

the address of interrupt handler (16 bits) A local mask-bit to enable/disable specific

interrupts

Hardware fixed priority One interrupt source can be elevated to the

Highest priority


CPU12, Interrupts, Vector table


Event from programmable interface

If locally enabled AND globally enabled (CCR:I = '0')

IRQ to the processor

else main program continue

HC12 Interrupts(Request)

In the initialization stage, the Interrupt routine address has to be programmed in the vector table. The address in the table is specified by the processor manufacturer.

locally enabled : Interrupt enable bit in the programmable interface

globally enabled : bit I in the Condition Code Register = ‘0’, CCR:I = '0'


μP (hardware):

Save I mask to temporary bit, mask globally the Interrupts Request I='1'

Search for the interrupt routine address in the vector table

Save all processor registers (μP context) on stack :

A, B, IX, IY, PC and CCR

Go to the interrupt routine : interrupt routine address PC

Interrupt routine (software) :

Execute the function

ACKNOWLEDGE the interrupt request, generally in the programmable interface

Return with special instruction RTE (ReTurn from Exception)

HC12 Interrupts (IRQ accepted)


μP (hardware) :

Restore the context :

Restore the processor register from the stack (including I flags and PC)

Continue the main program

HC12 Interrupts (return)


Parallel Ports

The μC input-output are grouped by PORT of 8-bits (usually).

They are divided into 2 modes : Parallel Port with the direction (Input / Output)

generally programmable Specific Interface (ATD; PWM; Timer; address,

data, control extension, etc ...)

Selected by the user (the programmer)


Parallel PortsName // direction Specialized functionPORTAD In A/D 8 channels 10 bits

PORTT I/O Timer

PORTS I/O Serial: SCI, SPI, 2 I/O

PORTP I/O 4 PWM, 4 I/O

PORTCAN I/O CANBUS, 5 I/O

PORTA I/O Addresses/Data

PORTB I/O Addresses/Data

PORTE I/O In PE<1..0>

Controls


Parallel Ports

Registres de contrôle des ports Registre de direction DDRx (Data Direction

Register x) Registre de données PORTx


A parallel Port Model (1 bit)

Pin I/O x

DDR

RegPortPar

PortPar

DxClk

WrDDR

WrPort

RdDDR

RdPort


ATD: A/D Converter

An ATD (Analog To Digital Converter) transforms a continuous analog signal to a numerical value. This value can be processed by the μP.

The ATD of μC HC12 has the following features : 1 serial converter 8 multiplexed channels 8 or 10 bits resolution 8 x 16 bits registers for the results : ATD0..ATD7 Modes:

1 conversion on 4 or 8 channels Continuous scan Multiples scan on 1 channel


HC12 Programmable Interface

ATD: A/D Converter

From Analog world to Digital World

1 Serial converter

8 external Inputs


ATD: A/D Converter

8 AnalogInput

Voltage Reference :

0x00 VRL

0xFF VRH

Result Registers

Serial AD converter


ATD: A/D Converter

ATDCTL0 et 1 : Reserved

ADR0H..ADR7H :8 Result registers 8 bits

ATDCTL0..ATDCTL5 :6 Control Registers (8 bits)

ATDSTAT :1 status Register (16 bits)

PORTAD :1 Input Port register

ADR0..ADR7 :8 Result registers 16 bits


ATD: A/D Converter

ADPU : 1: Enable ATD module AFFC : 1: ATD Fast Flag Clear: Clear ATDSTAT:CCF when

reading ADRx

0: Need to read ATDSTAT before AWAI : 1: Stop if mode WAIT ASCIE : 1: ATD Interrupt enable ASCIF : (read only) Flag conversion complete


ATD: A/D Converter

What happen if breakpoint arrives ?


ATD: A/D Converter

S10BM 1: 10 bits, 0: 8 bits SMP1, SMP0 Sampling delay PRS4..PRS0 Clock for ATD : between 500 kHz & 2 MHz

ATDClk = PCLK / ( 2 * PRSx + 1 )

PClk = fQuartz/2


ATD: A/D Converter

Sampling delay :


ATD: A/D Converter

S8CM 0 : 4 conversions, 1: 8 conversions SCAN 0 : 1 sequence of 4/8 conversions

1 : continuous of 4/8 sequences MULT 0 : 4/8 conversions simple channel CD..CA

1 : 4/8 conversions on 4/8 channels


ATD: A/D Converter

Channels 0xC, 0xD, 0xE & 0xF (12..15) for tests

A write to ATDCTL5 starts a conversion sequence


ATD: A/D Converter

SCF Sequence Complete Flag CC<2..0> Active Sequence Number CCF7..CCF0 Conversion Complete Flag

1 by ADRx Register


ATD: A/D Converter

SCF, CCF7..CCF0 : Activated ('1') when corresponding conversion is

terminated Cleared ('0'), depend on the state of bit ATDCTL2:AFFC :

AFFC is: 0 1

SCF / CCFx

Are cleared by :

Write ATDCTL5 start a new conversion

Read first result ADRx

Read ATDSTAT, followed by ADRx

Reading register ADRx


ATD: A/D Converter

One bit per input Attention: reading this registry can cause a

disturbance on the conversion of analog signal


ATD: A/D Converter

Conversion results: ADRxH x: 0..7

Result in 8 bits ADRx

Result in 10 bits mode : bits 15..6; bits 5..0 0


ATD: A/D Converter

As the converter made 4 or 8 contiguous conversions, the first result is in ADR0 register(s) and so on.

Independently of the starting register number.



PWM

Pulse Width Modulation

A way to do Digital to Analog Conversion


PWM

At start the PWM output is at '0' The module counts the input clock

At the programmed Duty value the output rise @ '1' At the programmed Period value the output return @ '0'

and the counter is Reset

The clock P is divided by the PWM prescaler (2 levels) and increments the PWM counter


PWM

The 4x PWM counter, Duty and Period registers are on 8 bits

PWM0 and PWM1, PWM2 and PWM3 can be concatenated to be 16 bits width.


PWM

Left Aligned Mode


PWM

Centered mode


PWM

The Quartz frequency is first divide by 2, 4, 8, 16, 32, 64 or 128 This is the first prescaler stage

This frequency can then by divided by 2, 4, 6, 8, 10, …512: every even value from 2 to 512 This is the second prescaler stage

2 full prescalers exist: 1 for PWM0/PWM1 and 1 for PWM2/PWM3


PWM, Clocks

Group PWM0 and PWM1

Group PWM2 and PWM3


PWM, Register PWCLK

CON23, CON01 1: PWM23 / PWM01 2 x16 bits

0: 4 x 8 bits PCKA<2..0> Prescalers PCKB<2..0>


PWM, Register PWPOL

PCLKx Clock Source 0: Clock A : PWM0 & 1

Clock B : PWM2 & 3 1: S0 : PWM0 & 1

S1 : PWM2 & 3

PPOLx PWM polarity


PWM, Register PWEN

PWENx Enable PWMx on Port P

PWMx is output, independently of DDRP


PWM, Register PWPRES

First Prescaler of clocks A & B


PWM, Registre prescaler

PWSCAL0/1 2nd prescaler 0 et 1, divide by 2512

PWSCNT0/1 Count value of 2nd prescaler


PWM, Registers PWCNT0..3

Counters PWMx (0..3) value


PWM, Registers PWPERx-PWDTYx


PWM, Duty cycle


PWM, Register PWCtl

PSWAI Wait mode -> stop clk generator

CENTR Mode centered (1), Aligned (0) RDP Reduction Power on P (1) PUPP Pull-up Enable Port P (1) PSBCK Disable PWM if BDI active (1)


PWM, Registers for PORT P

Direction 0: input

1: output


PWM, exercise

How to initialize the clock prescaler & PWMPeriod for: Quartz = 16 MHz PWM period = 250 μs Duty Resolution is 1 μs

fquartz fPWM01st prescaler

2nd prescaler

PWM:• Period• Duty

PWM0



Clock

How to distribute clock along the chip


Clocks


Divider for SCI RTI COP

Clock


Divider for Timer

Clock



RTI

Real Time Interrupt

A simple periodic interrupt


Real Time Interrupt

The Real Time Interrupt interface allows the uC to be interrupted periodically.The period is selectable in a configuration register RTICTL with the RTR<2..0> bits.Period = 212+RTR with RTR<2..0> = 000 RTI OFFPeriod = 23+RTR with RTBYP = '1' (Bypass predivider)

RTIE Real Time Interrupt Enable, allow interrupt generation at the end of the RTR time-out


RTR2 RTR1 RTR0 Divide by

Time-Out with E=8MHz

Quart=16MHz

0 0 0 OFF OFF

0 0 1 213 1.024 ms = 1'024 μs

0 1 0 214 2.048 ms

0 1 1 215 4.096 ms

1 0 0 216 8.192 ms

1 0 1 217 16.384 ms

1 1 0 218 32.768 ms

1 1 1 219 65.536 ms

Real Time Interrupt


Real Time Interrupt

At the end of Time-Out, a flag is activated in RTIFLG register:RTIF Real Time Interrupt Flag

If RTICTL:RTIE is activated ('1'), an interruption can be generated and accepted by the processor if CCR:I allow it

The request is deactivated by writing a '1' in RTIF:

RTIFLG = 0x80; // C instruction to clear RTIFLG

R.Beuchat Interruptions 81

HC12 Interrupts (recall )

General Mask: bit I Flags register I=0 Interrupts enabled (instruction CLI: Clear I) I=1 Interrupts disabled (instruction SEI: Set I)

Individual Interrupts masks One bit by interrupt source

Event

Clear IRQlocal (Write «1»)

IRQ Local

Enable Local Interrupt

IRQ uP

IRQ a

IRQ x

IRQ b

CCR Flags: I

IRQ …


CPU12, Interrupts

Priority



Timer

How to manage Input/Output

related to time


Timer, Pulse Accumulator

TCNT : Free CounterTIOC : Input Capture /

Output Compare


Timer TCNT : Free CounterTIOC : Input Capture /

Output Compare


Timer, Output Compare

Activation of Output TOC when Counter = TIOC


Output Compare


TimerMode Output Compare

TCNT

t

FFFF

0000

TOCxTCNT = TOCx

TFLG1:CxF

External effect on TCx, depends of TCTL1,2SortieTCx


Output Compare


Timer, Input Capture

Active Transition


Output Compare

Time of transition is

registered in TIOC


TimerMode Input Capture

TCNT

t

FFFF

0000

TIOCx

TCx =TCNT

TICx

External event on sur TCx

TFLG1:CxF

TCx =TCNT


Timer, registersparallel port mode

The port can be used in parallel port mode. The direction of each bit is programmable. This mode can be used simultaneously with

the timer mode if: The corresponding pin is in "input capture" or The corresponding pin is in "output compare"

without changing the output function, output compares with only the activation of TFLG1 used


Timer, registersmode parallel port

PORTT 0x00AE Port T data Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reset : 0 0 0 0 0 0 0 0

Data Register in I/O mode

DDRT 0x00AFPort P direction

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reset : 0 0 0 0 0 0 0 0

Direction Register in I/O mode :0 : mode input, 1 : mode output


Timer, registresInput Capture or Output Compare

TIOS 0x0080

Timer Input Capture/Output Compare Select

IOS7

IOS6

IOS5

IOS4

IOS3

IOS2

IOS1

IOS0

Reset : 0 0 0 0 0 0 0 0

IOS<7..0>0 Input Capture

1 Output Compare

If the timer mode is used, specify the mode: • input capture ('0') / output compare ('1')


Timer, registersOutput action in Output compare mode

TCTL1 0x0088 Timer Control OM7

OL7

OM6

OL6

OM5

OL5

OM4

OL4

TCTL2 0x0089 Timer Control OM3

OL3

OM2

OL2

OM1

OL1

OM0

OL0

Reset : 0 0 0 0 0 0 0 0

OMx OLx

Select output action in output modeTIOSx = ‘1’

00Timer pin not used, PORTT & DDRT used

01 toggle the Output x ()

10 Output x @ ”0”

11 Output x @”1”


Timer, registersselect active edge in Input capture mode

TCTL3 0x008A Timer Control

EDG7B

EDG7A

EDG6B

EDG6A

EDG5B

EDG5A

EDG4B

EDG4A

TCTL4 0x008B Timer Control

EDG3B

EDG3A

EDG2B

EDG2A

EDG1B

EDG1A

EDG0B

EDG0A

Reset : 0 0 0 0 0 0 0 0

EDGxB EDGxA

Select output action in input modeTIOSx = ‘0’

00 No edge Capture

01 Capture on rising edge

10 Capture on falling edge

11 Capture on both edge


Timer, registersselect active edge in Input capture mode

The programmed transition on pin x memorized le time from TCNT in the corresponding TCx register

The bit x of TFLG1 is activated If enabled by TMSK1 & CCR:I, an interrupt

is generated


Timer, registresEvent Flags 1

TFLG1 0x008E Timer Flag 1 C7F C6F C5F C4F C3F C2F C1F C0F

Reset : 0 0 0 0 0 0 0 0

C<7..0>F flag bit

0 No new event

1 Event

• To clear the event flag, a '1' has to be written in the corresponding bit. Writing a '0' has NO effect.• If the TFFCA bit in the TSCR register is @ '1', a write to the TCx register in OC mode, or a read of TCx in IC mode, clear the corresponding CxF bit of TFLG1.• The event can generate an interrupt if enabled in TMSK1.


Timer, registresEvent Flags 2

.TFLG20x008F

Timer Flag 2

TOF 0 0 0 0 0 0 0

Reset : 0 0 0 0 0 0 0 0

TOFTimer OverFlow

0 -

1Passage of 0xFFFF 0x0000 on TCNT

An access on TCNT but the TOF @ '0' if TFFCA in the TSCR register is @ '1'.Or a write access of 0x80 in TFLG2 .


Timer, registresInterrupt mask

.

TMSK1 0x008CTimer Mask 1 C7I C6I C5I C4I C3I C2I C1I C0I

Reset : 0 0 0 0 0 0 0 0

C<7..0>I Mask bit

0 Interrupt disable

1 Interrupt enable


Timer, registersInterrupt mask and controls

.

TMSK2 0x008D Timer Mask 2TOI 0

PUPT

RDPT

TCRE

PR2 PR1 PR0

Reset : 0 0 0 0 0 0 0 0

TOI Timer OverFlow mask0 Interrupt disable

1 Interrupt enable

PUPTTimer Pull-Up Resistor Enable

0 No pull-up

1 Pull-up in input capture mode

RDPTTimer Drive Reduction

0 Normal output Courant

1 Reduced output Courant

TCRETimer Counter Reset Enable

0 Counter in free runnng mode

1 Counter cleared on OC7 activation

PR<2..0>Prescaler between (Quartz/2) et module timer clock

000 /1

001 /2

010 /4

011 /8

100 /16

101 /32

110 -

111 -


Timer, registersValues to compare, capture

.

TC0 0x0090

Timer Compare/Capture

Bit15

0x0091Bit0

…

TC7 0x009E

Timer Compare/Capture

Bit15

0x009F Bit0

TCNT state memorized in case of input captureComparison time in output compare mode


Timer, registerStatus and control

.

TSCR 0x0086 Timer Input Capture/Output Compare Select

TENTSW

AITSBCK TFFA 0 0 0 0

Reset : 0 0 0 0 0 0 0 0

TEN Timer Enable0 Timer disable

1 Timer enable

TSWAI0 Timer run in state WAIT

1 Timer stopped in state WAIT

TSBCK0 Timer run in BackGround mode

1 Timer stop in BackGround mode

TFFA

0 Clear flags with '1' writing

1Clear flags directly in event register access (TCx, TCNT)


OC7D 0x0083

Output Compare 7 Data Register

OC7D 7

OC7D 6

OC7D 5

OC7D 4

OC7D 3

OC7D 2

OC7D 1

OC7D 0

Reset :0 0 0 0 0 0 0 0

OC7D<7..0> Data value

0“0” on PORTTx, if OC7 activated and OC7Mx=1

1“1” on PORTTx, if OC7 activated and OC7Mx=1

Timer, registerssynchronization of timer 7 on others Output

.

OC7M 0x0082 Output Compare 7 Mask Register

OC7M 7

OC7M 6

OC7M 5

OC7M 4

OC7M 3

OC7M 2

OC7M 1

OC7M 0

Reset : 0 0 0 0 0 0 0 0

OC7M<7..0> Mask bit

0 No action from OC7

1 OC7 activated has an action on x bit



Serial communication

SCI, Serial Communication Interface

SPI, Synchronous Peripheral Interface


Serial Ports

SCI : Serial Communication Interface

SPI : Synchronous Peripheral Interface


Asynchronous, SCI


Synchronous, SPI


CAN Bus

RBMicrocontroller HC12 1 Microcontrollers General 8 bits μControllers Example : 68HC912BC32...

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