CMPEN 411VLSI Di it l Ci itVLSI Digital Circuits

Spring 2011

Lecture 12: Logical Effort

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

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PMOS/NMOS Ratio Effects

5 x 10-11

β = (W/Lp)/(W/Ln)

t t4.5

tpLH tpHL

β of 2.4 (= 31 kΩ/13 kΩ) gives symmetrical

3

4 tp response

β of 1 6 to 1 9 gi es

3

3.5 β of 1.6 to 1.9 gives optimal performance

31 2 3 4 5

β = (W/Lp)/(W/Ln)

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Example of Inverter Chain Sizing

In Out1

CL = 8 Cg,1Cg,1

1

CL/Cg,1 has to be evenly distributed over N = 3 inverters

F = CL/Cg,1 = 8/1

f =

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Heads upThis lectureThis lecture

Logical Effort - Reading assignment – textbook pp251-257, and handout

Next lectureDesigning energy efficient logic

R di i R b l & 6 2 1- Reading assignment – Rabaey, et al, 5.5 & 6.2.1

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History

First proposed by Ivan Sutherland and Bob Sproull in 1991

“Logical Effort: Designing for Speed on the back of an Envelope”, IEEE Advanced Research in VLSI, 1991Both authors are vice president and fellow at SunBoth authors are vice president and fellow at Sun

Microsystems

Gain-based synthesis based on Logical effort y gImplemented in IBM’s logic synthesis tool BooleDozer Also adopted by Magma’s logic synthesis tool

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Inverter DelayDivide capacitive load C intoDivide capacitive load, CL, into

Cint : intrinsic - diffusion and Miller effect (Cg)Cext : extrinsic - wiring and fanout

tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint)=0.69(ReqCint + ReqCext)

where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the gate

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Logical Effort Delay Model

Delay of logic gate has two componentsd = f + p

f: effort delayp: parasitic delay

Effort delay fg has two components:Effort delay fg has two components:f=gh

g: logical effort h: electrical effort = Cout/ Cin (the ratio of

output capacitance to input capacitance)

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Gate Delay Components

C

Logic

Cin

Cout

Split delay of logic gate into three components

Delay = Logical Effort x Electrical Effort + Parasitic Delay

gGate

Delay Logical Effort x Electrical Effort + Parasitic Delay

Logical EffortComplexity of logic function (Invert, NAND, NOR, etc)Define inverter has logical effort = 1Depends only on topology not transistor sizing

Electrical EffortElectrical EffortRatio of output capacitance to input capacitance Cout/Cin

Parasitic Delay

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Intrinsic delayIndependent of transistor sizes and output load

Computing Logical Effortg represents the fact that for a giveng represents the fact that, for a given load, complex gates have to work harder than an inverter to produce a similar (speed) response(speed) response

the logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more inputan inverter (how much more input capacitance a gate presents to deliver the same output current)

Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering capac ta ce o a e te de e gthe same output current

Defined to be 1 for an inverter

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Computing Logical Effort

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Logic Gate Delay

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Logic Gate Delay

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ExampleE ti t th d l f i t d i i 4 id ti lEstimate the delay of an inverter driving 4 identical inverter: (FO4)

g= h= p= d=

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Example

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Path Delay of Complex Logic Gate NetworkT t l th d l th h bi ti l l i bl kTotal path delay through a combinational logic block

tp = ∑ dj = ∑pj + ∑hj gj

th i i d l th h th th d t i th t h tthe minimum delay through the path determines that each stage should bear the same gate effort

h1g1 = h2g2 = . . . = hNgN

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Application of Logical Effort

Alternative logic structures, which is the fastest?

F = ABCDEFGH

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Application of Logical Effort

Alternative logic structures, which is the fastest?

F = ABCDEFGHg1=10/3 g2=1

1 6/3 2 /3g1=4/3 g2=5/3 g3=4/3 g4=1

g1=6/3 g2=5/3

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Review: Design Technique 4f f f ffIsolating fan-in from fan-out using buffer insertion

CCLCL

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Questions

d = gh+p

How to derive the model from Elmore delay model?How to derive the model from Elmore delay model?

Why logical effort g is independent of transistor sizing?

How to calculate parasitic delay p ? Why it is independent of transistor sizing?

How to calculate single delay parameter: τ

What if the ratio of p-type to n-type transistor widths changes?

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From Elmore model to Logical Effort Model

RR

CinCin CpCp CoutCout

Elmore Delay = R(Cp+Cout)Elmore Delay = R(Cp+Cout)Elmore Delay R(Cp Cout)Elmore Delay R(Cp Cout)= R*Cout + R*Cp= R*Cout + R*Cp= RCin*(Cout/Cin)+R*Cp= RCin*(Cout/Cin)+R*Cp

gg hh

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gg hh pp

Parasitic Delay

Main cause is drain capacitances

Th l ith t i t idthCgateP

These scale with transistor width so it is independent of transistor sizesCdrainPRonP

For inverter:onP

Parasitic Delay ~= 1.0 τCdrainN

RonN

CgateN

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How to calculate single delay parameter: τ

Ch t i d ith i l d l tCharacterize process speed with single delay parameter: τ

τ ~= 15 ps for 0.18um ~=20 ps for 0.25 um

How to estimate it for a new process? (such as 0.13 or 0.09 um)How to estimate it for a new process? (such as 0.13 or 0.09 um)

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Inverter Chain Delay

For each stage:

Delay = Logical Effort x Electrical Effort + Parasitic Delay

= 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps)

= 2.0 units 2.0 units

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Multistage Logic Network

Path logical effort, G = Π gi (gi = L.E. stage i)

Path electrical effort, H = Cout/Cin (hi = E.E. stage i)

P iti d l P Σ ( P D t i)Parasitic delay, P = Σ pi (pi = P.D. stage i)

Path effort, F= Π fi = Π gi hi

D F+PD= F+P

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Paths that BranchCConsider paths that branch:

G =

H = 5

1590

GH =

h =

5

1590h1 =

h2 =

F = GH?

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Paths that BranchCNo! Consider paths that branch:

G = 1

H = 90 / 5 = 18 5

1590

GH = 18

h = (15 +15) / 5 = 6

5

1590h1 = (15 +15) / 5 = 6

h2 = 90 / 15 = 6

F = g1g2h1h2 = 36 = 2GH

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Add Branching Effort

Branching effort:

pathon

pathoffpathonC

CCb

−

−− +=

pathon

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Multistage Networks

Path electrical effort: H= Cout/Cin

Path logical effort: G = g1g2 gNPath logical effort: G = g1g2…gN

Branching effort: B = b1b2…bN

P th ff t F GBHPath effort: F= GBH

Path delay D = F+P=GBH+P

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Optimal Number of Stages

Cin

C t

Minimum delay when:

stage effort = logical effort x electrical effort = 3 4-3 8 ~ 4

Cout

stage effort = logical effort x electrical effort = 3.4-3.8 4

Fan-out-of-four (FO4) is convenient design size (~5τ)

FO4 delay: Delay of inverter driving four

copies of itself

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Method of Logical EffortC ff GCompute the path effort: F = GBH

Find the best number of stages N ~ log4 F

Compute the stage effort f = F1/N

Sketch the path with this number of stagesp g

Work either from either end, find sizes: Cin = Cout*g/f

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Example of Inverter (Buffer) StagingN f t

C 64 CC 1

1

N f tp

1 64 65CL = 64 Cg,1Cg,1 = 1

1 8 2 8 18CL = 64 Cg,1Cg,1 = 1

4 16

2 8 18

3 4 15CL = 64 Cg,1Cg,1 = 1

1 4 16 3 4 15

CL = 64 Cg,1Cg,1 = 1

1 2.8 8 22.6 4 2.8 15.3

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Summary

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Next Lecture and RemindersNext lectureNext lecture

Designing energy efficient logic - Reading assignment – Rabaey, et al, 5.5 & 6.2.1

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