EE 466/586 VLSI Design

Partha Pande School of EECS

Washington State University pande@eecs.wsu.edu

Lecture 22 Arithmetic circuits (Cont’d)

Manchester Carry Chain

CoCi

Gi

Di

Pi

Pi

VDD

CoCi

Gi

Pi

VDD

φ

φ

The propagate path passes Ci to Co output if the propagate signal is true If the propagate condition is not satisfied, the output is either pulled low by the Di signal or pulled up by

Gi

Manchester Carry Chain

G2

φ

C3

G3Ci,0

P0

G1

VDD

φ

G0

P1 P2 P3

C3C2C1C0

Carry-Bypass Adder

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co,2Co,1Co,0Ci,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

Co,3

Mul

tiple

xer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.

Also called Carry-Skip

Carry-Bypass Adder (cont.)

Carrypropagation

SetupBit 0–3

Sum

M bits

tsetup

tsum

Carrypropagation

SetupBit 4–7

Sum

tbypass

Carrypropagation

SetupBit 8–11

Sum

Carrypropagation

SetupBit 12–15

Sum

Carry-Bypass Adder (cont.)

Total adder is divided into (N/M) length bypass stages, each of which contains M bits.

tadder = tsetup + Mtcarry + (N/M-1)tbypass + tsum

tsetup= Fixed overhead time to create the generate and propagate signals

tcarry= Propagation delay through a single bit. The worst case carry propagation delay through a single stage of M bits is approximately M times larger.

tbypass=the propagation delay through the bypass multiplexer of a single stage.

tsum= the time to generate the sum of the final stage.

Carry Ripple versus Carry Bypass

N

tp

ripple adder

bypass adder

4..8

Linear Carry-Select Adder

Anticipate both possible values of the carry input and evaluate the result for both possibilities in advance.

Once the real value of the incoming carry is known, the correct result is selected with a multiplexer stage.

Carry-Select Adder Setup

"0" Carry Propagation

"1" Carry Propagation

Multiplexer

Sum Generation

Co,k-1 Co,k+3

"0"

"1"

P,G

Carry Vector

Carry Select Adder: Critical Path

0

1

Sum Generation

Multiplexer

1-Carry

0-Carry

Setup

Ci,0 Co,3 Co,7 Co,11 Co,15

S0–3

Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15

0

1

Sum Generation

Multiplexer

1-Carry

0-Carry

Setup

S4–7

0

1

Sum Generation

Multiplexer

1-Carry

0-Carry 0-Carry

Setup

S8–11

0

1

Sum Generation

Multiplexer

1-Carry

Setup

S12–15

Linear Carry Select

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

S0-3 S4-7 S8-11 S12-15

Ci,0

(1)

(1)

(5)(6) (7) (8)

(9)

(10)

(5) (5) (5)(5)

Square Root Carry Select Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

S0-1 S2-4 S5-8 S9-13

Ci,0

(4) (5) (6) (7)

(1)

(1)

(3) (4) (5) (6)

Mux

Sum

S14-19

(7)

(8)

Bit 14-19

(9)

(3)

Adder Delays - Comparison

Square root select

Linear select

Ripple adder

20 40N

t p(in

uni

t del

ays)

600

10

0

20

30

40

50

LookAhead - Basic Idea

Co k, f A k Bk Co k, 1–, ,( ) Gk P kCo k 1–,+= =

AN-1, BN-1A1, B1

P1

S1

• • •

• • • SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A0, B0

Look-Ahead: Topology

Co k, Gk Pk Gk 1– Pk 1– Co k 2–,+( )+=

Co k, Gk Pk Gk 1– P k 1– … P1 G0 P0 Ci 0,+( )+( )+( )+=

Expanding Lookahead equations:

All the way:

Co,3

Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2

G3

Look-Ahead: Topology

Co k, Gk Pk Gk 1– Pk 1– Co k 2–,+( )+=

Co k, Gk Pk Gk 1– P k 1– … P1 G0 P0 Ci 0,+( )+( )+( )+=

Expanding Lookahead equations:

All the way:

Logarithmic Look-Ahead Adder

A7

F

A6A5A4A3A2A1

A0

A0A1

A2A3

A4A5

A6

A7

F

tp∼ log2(N)

tp∼ N

Carry Lookahead Trees

Co 0, G0 P0Ci 0,+=

Co 1, G1 P1 G0 P1P0 Ci 0,+ +=

Co 2, G2 P2G1 P2 P1G0 P+ 2 P1P0Ci 0,+ +=

G2 P2G1+( )= P2P1( ) G0 P0Ci 0,+( )+ G 2:1 P2:1Co 0,+=

Can continue building the tree hierarchically.

Carry Lookahead Trees

The carry-propagation process is decomposed into subgroups of two bits Gi:j and Pi:j denote the generate and propagate functions,

respectively, for a group of bits for positions I to j Block generate and propagate signals. Gi:j equals 1 if the group generates a carry, independent of

the incoming carry The block propagate Pi:j is true if an incoming carry

propagates through the complete group.

Example: Domino Adder

VDD

Clk Pi= ai + bi

Clk

ai bi

VDD

Clk Gi = aibi

Clk

ai

bi

Propagate Generate

Example: Domino Adder

VDD

Clkk

Pi:i-k+1

Pi-k:i-2k+1

Pi:i-2k+1

VDD

Clkk

Gi:i-k+1

Pi:i-k+1

Gi-k:i-2k+1

Gi:i-2k+1

Propagate Generate

Example: Domino Sum