Lecture 14: Circuit Families - Home | University of...

Introduction to CMOS VLSI

Design

Lecture 14: Circuit Families

David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan

University of Pittsburgh

CMOS VLSI Design 9: Circuit Families Slide 2

Outline q  Pseudo-nMOS Logic q  Dynamic Logic q  Pass Transistor Logic


Introduction q  What makes a circuit fast?

–  I = C dV/dt -> tpd ∝ (C/I) ΔV –  low capacitance –  high current –  small swing

q  Logical effort is proportional to C/I q  pMOS are the enemy!

–  High capacitance for a given current q  Can we take the pMOS capacitance off the input? q  Various circuit families try to do this…

BA

11

4

4

Y


Pseudo-nMOS q  In the old days, nMOS processes had no pMOS

–  Instead, use pull-up transistor that is always ON q  In CMOS, use a pMOS that is always ON

–  Ratio issue –  Make pMOS about ¼ effective strength of

pulldown network

Vout

Vin16/2

P/2

Ids

load

0 0.3 0.6 0.9 1.2 1.5 1.80

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout


Pseudo-nMOS Gates q  Design for unit current on output

to compare with unit inverter. q  pMOS fights nMOS

Inverter NAND2 NOR2

AY

B

AY

A B

gu =gd =gavg =pu =pd =pavg =

Y



finputs

Y




Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3


Y



finputs

Y




Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3gd = 4/9gavg = 8/9pu =pd =pavg =

Y



finputs

Y




Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9

Y



finputs

Y


Pseudo-nMOS Design q  Ex: Design a k-input AND gate using pseudo-nMOS.

Estimate the delay driving a fanout of H

q  G = q  F = q  P = q  N = q  D =

In1

Ink

Y

Pseudo-nMOS1

1 H


Pseudo-nMOS Design q  Ex: Design a k-input AND gate using pseudo-nMOS.

Estimate the delay driving a fanout of H

q  G = 1 * 8/9 = 8/9 q  F = GBH = 8H/9 q  P = 1 + (4+8k)/9 = (8k+13)/9 q  N = 2 q  D = NF1/N + P =

In1

Ink

Y

Pseudo-nMOS1

1 H

4 2 8 133 9H k ++


Pseudo-nMOS Power q  Pseudo-nMOS draws power whenever Y = 0

–  Called static power P = I•VDD

–  A few mA / gate * 1M gates would be a problem –  This is why nMOS went extinct!

q  Use pseudo-nMOS sparingly for wide NORs q  Turn off pMOS when not in use

A BY

C

en


Dynamic Logic q  Dynamic gates uses a clocked pMOS pullup q  Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

φ

Static Pseudo-nMOS Dynamic

φ Precharge Evaluate

Y

Precharge


The Foot q  What if pulldown network is ON during precharge? q  Use series evaluation transistor to prevent fight.

AY

φ

foot

precharge transistor φY

inputs

φY

inputs

footed unfooted

f f


Logical Effort Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd =pd =

gd =pd =

gd =pd =

Yφ

φ

φ

2

1

AY

3

3

1

B

AY

A B 22

1

gd =pd =

gd =pd =

gd =pd =

Yφ

φ

φ

footed

unfooted

32 2


Logical Effort Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd = 1/3pd = 2/3

gd = 2/3pd = 3/3

gd = 1/3pd = 3/3

Yφ

φ

φ

2

1

AY

3

3

1

B

AY

A B 22

1

gd = 2/3pd = 3/3

gd = 3/3pd = 4/3

gd = 2/3pd = 5/3

Yφ

φ

φ

footed

unfooted

32 2


Monotonicity q  Dynamic gates require monotonically rising inputs

during evaluation –  0 -> 0 –  0 -> 1 –  1 -> 1 –  But not 1 -> 0


Y

Precharge

A

Output should rise but does not

violates monotonicity during evaluation

A

φ


Monotonicity Woes q  But dynamic gates produce monotonically falling

outputs during evaluation q  Illegal for one dynamic gate to drive another!

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y


Monotonicity Woes q  But dynamic gates produce monotonically falling

outputs during evaluation q  Illegal for one dynamic gate to drive another!

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation


Domino Gates q  Follow dynamic stage with inverting static gate

–  Dynamic / static pair is called domino gate –  Produces monotonic outputs


W

Precharge

X

Y

Z

A

φ

B C

φ φ φ

C

AB

W X Y Z =X

ZH H

A

W

φ

B C

X Y Z

domino AND

dynamicNAND

staticinverter


Domino Optimizations q  Each domino gate triggers next one, like a string of

dominos toppling over q  Gates evaluate sequentially but precharge in parallel q  Thus evaluation is more critical than precharge q  HI-skewed static stages can perform logic

S0

D0

S1

D1

S2

D2

S3

D3

φ

S4

D4

S5

D5

S6

D6

S7

D7

φ

YH


Dual-Rail Domino q  Domino only performs noninverting functions:

–  AND, OR but not NAND, NOR, or XOR q  Dual-rail domino solves this problem

–  Takes true and complementary inputs –  Produces true and complementary outputs

sig_h sig_l Meaning 0 0 Precharged 0 1 ‘0’ 1 0 ‘1’ 1 1 invalid

Y_h

f

φ

φ

inputs

Y_l

f


Example: AND/NAND q  Given A_h, A_l, B_h, B_l q  Compute Y_h = A * B, Y_l = ~(A * B)


Example: AND/NAND q  Given A_h, A_l, B_h, B_l q  Compute Y_h = A * B, Y_l = ~(A * B) q  Pulldown networks are conduction complements

Y_hφ

φ

Y_lA_h

B_hB_lA_l

= A*B= A*B


Example: XOR/XNOR q  Sometimes possible to share transistors

Y_hφ

φ

Y_lA_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B


Leakage q  Dynamic node floats high during evaluation

–  Transistors are leaky (IOFF ≠ 0) –  Dynamic value will leak away over time –  Formerly miliseconds, now nanoseconds!

q  Use keeper to hold dynamic node –  Must be weak enough not to fight evaluation

A

φH

2

2

1 kX Y

weak keeper


Charge Sharing q  Dynamic gates suffer from charge sharing

B = 0

AY

φ

x

Cx

CY

A

φ

x

Y



B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

x YV V= =



B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V VC C

= =+


Secondary Precharge q  Solution: add secondary precharge transistors

–  Typically need to precharge every other node q  Big load capacitance CY helps as well

B

AY

φ

x

secondaryprechargetransistor


Noise Sensitivity q  Dynamic gates are very sensitive to noise

–  Inputs: VIH ≈ Vtn

–  Outputs: floating output susceptible noise q  Noise sources

–  Capacitive crosstalk –  Charge sharing –  Power supply noise –  Feedthrough noise –  And more!


Domino Summary q  Domino logic is attractive for high-speed circuits

–  1.5 – 2x faster than static CMOS –  But many challenges:

•  Monotonicity •  Leakage •  Charge sharing •  Noise

q  Widely used in high-performance microprocessors


Pass Transistor Circuits q  Use pass transistors like switches to do logic q  Inputs drive diffusion terminals as well as gates

q  CMOS + Transmission Gates: –  2-input multiplexer –  Gates should be restoring

A

B

S

S

S

Y

A

B

S

S

S

Y


LEAP q  LEAn integration with Pass transistors q  Get rid of pMOS transistors

–  Use weak pMOS feedback to pull fully high –  Ratio constraint

B

S

SA

YL


CPL q  Complementary Pass-transistor Logic

–  Dual-rail form of pass transistor logic –  Avoids need for ratioed feedback –  Optional cross-coupling for rail-to-rail swing

B

S

S

S

S

A

B

AY

YL

L

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