Analog and RF circuit techniques in nanometer CMOS
Bram Nauta University of Twente
The Netherlands http://icd.ewi.utwente.nl
b.nauta@utwente .nl
UNIVERSITY OF TWENTE.
Outline
• Introduction • Balun-LNA-Mixer (BLIXER) • Interferer robust SDR RX – analog part • Interferer robust SDR RX – digital part • Summary
3
ωLO
ωLO
Preferred: one wide band frontend IC: Software Defined
Keep minimal
4
RF system trend (I)
• Challenges wide band circuits:
Minimal pre-filtering: high linearity No high Q tanks: low noise • Bandwidth will be ok for low GHz
• Towards Software Defined Radio
Outline
• Introduction • Balun-LNA-Mixer (BLIXER) • Interferer robust SDR RX – analog part • Interferer robust SDR RX – digital part • Summary
6
BLIXER
Balun + LNA + Mixer
[Blaakmeer, ISSCC2008]
7
ωLO
ωLO
BLIXER=Wide band receiver
8 8
Balun-LNA Simultaneous: • Single-to-Differential • Balanced Gain • Broadband input
match ( ~1/gmCG ) • Noise Canceling • Distortion Canceling
[Blaakmeer et al. ESSCIRC `07]
RS vs
vin +
-
vout + -
CG CS
IBias
9 9
Noise Canceling
vin +
- Ibias
in
50Ω
20mS
80mS
200Ω 50Ω
vs
10 10
Bandwidth problem:
vin +
- Ibias
50Ω
20mS
80mS
200Ω 50Ω
vs
C < 80fF for BW=10GHz
11 11
So, Don’t make voltage gain @ RF
vin +
- Ibias
50Ω
20mS
80mS
200Ω 50Ω
vs
12 12
Use a MIXER
vin +
- Ibias
50Ω
20mS
80mS
200Ω 50Ω
vs
13 13
RS vs
RF: no high-Z nodes
Now Low frequency
Low-Z
LO
gm
4·gm
Z 4·Z
IBias
14 14
Mixer stacked on CG-CS stage
gm·vrf 4·gm·vrf
vs
RS
W 4·W
IF+ IF-
LO+ LO-
Z 4·Z
R
3·R
3·C
C
vrf + -
‘CG’ ‘CS
’
[Blaakmeer, ISSCC’08]
15 15
Chip Micrograph and PCB detail
Baseline 65nm CMOS 1.2V supply Active area < 0.02 mm2
OSC
IN IF Out Lbias
OSC
IN
IF I+ IF I-
IF Q+ IF Q-
Supply & Biasing
LO gen + buf Core + IF-buf Biasing
1.4 mm
16
Conversion Gain, NF and S11
16 RX-frequency [GHz]1 10
[dB]
-30
-20
-10
0
10
20GC
NF
S11 fIF = 50 MHz
7GHZ
17 17
Other BLIXER Performance
• Linearity: – IIP3 @ RF: -3 dBm – IIP2 @ RF: +20 dBm
• Quadrature accuracy: – Phase error < 3° – Gain error < 1dB
• LO leakage < -50 dBm • Dissipation
– 33mW (LO=500MHz) – 57mW (LO=7GHz)
Outline
• Introduction • Balun-LNA-Mixer (BLIXER) • Interferer robust SDR RX – analog part • Interferer robust SDR RX – digital part • Summary
A Software-Defined Radio Receiver Architecture
Robust to Out-of-Band Interference
[Ru, ISSCC 2009]
20
ωLO
ωLO
21
Conventional Multi-Band Receiver
• RF filters for out-of-band interference, but bulky, costly, lossy, inflexible… • Our goal: Software Defined Radio with relaxed RF filtering
…
Chip
850M
900MLNA
LNA
LNA
LNA
Ante
nna
Switc
hes
IFA
LPF
IFA
LPF1800M
1900M
0/90° LO
…
!
22
Wideband Interfering: Nonlinearity
• Wideband LNA: also amplifies interference à nonlinearity
-50dBm
+10dBm
0.8G 1.6G 2.4G
-20dBm
3.2G
-70dBm-10dBm
0.8G 1.6G
Wanted Interference
2.4G
-40dBm
LNAA B C 0.8G 2.4G
...WidebandGain=20dB
Intermodulation & blocking
23
Wideband Interfering: Harmonic Mixing
• Switching mixer: square-wave LO à harmonic mixing
LNAA B C 0.8G 2.4G
...WidebandGain=20dB
-70dBm -40dBm
0.8G 2.4G
-50dBm
DC
-30dBm-50dBm-20dBm
0.8G 2.4G
Wanted 3rd harmonic
24
Concept: Use LP Filtering for Selectivity
• Voltage gain only at BB after low-pass filter (LPF) to filter blockers à Keep low impedance over a wide band at node B
V-IA B C
I-V
LO
LNA1st node with voltage gain
Baseband (BB)
RFLPF
50Ω
Low Gain,Low Pain.
25
Realization: Wideband LNTA + Mixer + TIA
• LNTA: high Gm & high Rout à low noise small voltage swing at node B à good linearity • Similar to [1], but now wideband and with blocker filtering
[1] Redman-White & Leenaerts, ESSCIRC07
LNTAA B C
OTAD
LO
RF BB50Ω
Impe
danc
e
f
≈+Rmixer
DCLO f
V-I LPF & I-V
26
Harmonic Rejection (HR) Mixer: Remove 3LO and 5LO
[2] Weldon et. al., ISSCC01
45°
1
1√2
3rd or 5th harmonic
: cancel!
√245°
1
1
1st or 7th harmonic
: add up!
• Amplitude weighting + phase shifting à emulate sine-LO
ÞLO3
LO2
LO1
x1
x√2
x1
Effective LO
1RF BB
Û
LO1
1
1
LO2
LO3
√2RF BB
-45°
0°
45°
1
1√2
Þ
27
Problem: Amplitude and Phase Errors
• Amplitude and phase errors à unwanted harmonic residue à degrade HR ratio • How to make irrational ratio, e.g. √2, on chip?
3rd or 5th harmonic vector diagram
Phase Error45°
1
1 √2
Δφ
residue
Amplitude Error45°
1
1 √2(1+α)residue
28
2-Stage Polyphase HR: Concept
• 41/29=1.4138, √2=1.4142 à ε=0.03%
1st Stage 2nd Stage
2
23
2
23
x2x3x2
x2x3x2
x2x3x2
0°
45°
-45°
0°45°90°
135°
45°90°
2
23
x7
x5
x5
29
2941
29
2-Stage Polyphase HR: Realization
• RF LNTA for 1st-stage weighting (2:3:2) • BB resistor for 2nd-stage weighting (5:7:5) • Nominally √2, what about influence of mismatch?
-+-+
-+-+
-+-+
-+-+
0°
45°
90°
135°
180°
225°
270°
315°
2Gm
2Gm
3GmRF+-
50Ω
50Ω Q+
-
-+-+
-+-+
I+
-
75
7
75
7
75
7
75
7LNTA
30
Reduced Effect of Amplitude Mismatch
• 2-stage polyphase à product of relative errors • E.g. 2:3:2 à α=6% à 1st-stage only: HR3=40dB 5:7:5 à β=1% à 2-stage total: HR3=86dB
3rd or 5th harmonic
1st
harmonic(desired signal)
45°
√2α·1
√2α·√2(1+β)
2αβ
√2α·1
√2(2+α)·√2(1+β)
2(2+α)(2+β)45°
√2(2+α)·1
√2(2+α)·1
2nd stage (error β in √2)
≈ratio α2 ·β2≈ratio
α2
45°
1
1√2(1+α)
√2α
√2(1+α)
√2(2+α)45°
1
1
1st stage (error α in √2)
31
• LP blocker filtering: attenuates interference around LO • 2-stage polyphase HR: robustly attenuates 3LO and 5LO
RF Filtering is Relaxed!
50ΩLNTARF BB
2:3:2 HR Mixer 757
OTA OTA
RF to BB Periodic Transfer Funciton (PXF)
LO 3LO 5LO 7LO fDC
17dBPXF (dB)
32
Zero-IF Receiver Prototype
2Gm
2Gm
3Gm
-+-+
-+-+
-+-+
-+-+
RF+-
Chip
Q+
-
8
-+-+
-+-+
I+
-
8CLK+-
50Ω
50Ω
100Ω
757
Clock
LNTA Mixer
TIA1
757
757
757
R-net
TIA2
33
Chip Photo
• 1mm2 in 65nm CMOS
• VDD: 1.2V • Current
consumption: – Analog 33mA – Digital 17mA
34
Measured HR: 40 Chips
• No trimming & calibration, no RF filtering
Min. HR3=60dBMin. HR5=64dB
10 20 30 401
60
70
80
90
Sample #
HR
Rat
io (d
B)HR Ratio @ 0.8G LO
5th3rd
35
Measured Performance Summary
VDD 1.2V Current
Consumption Analog: 33mA Digital (clock):
8mA @ 0.4GHz 17mA @ 0.9GHz
1 Out-of-band IIP3: two tones = 1.61G & 2.40GHz, LO = 819MHz 2 Out-of-band IIP2: two tones = 1.80G & 2.40GHz, LO = 601MHz
LO Frequency 0.4~0.9GHz Gain 34.4±0.2dB
DSB NF 4dB±0.5dB S11 < -10dB 80M~5.5GHz
In/Out-of-band IIP31
+3dBm / +18dBm
In/Out-of-band IIP22
+46dBm / +51dBm
IF Bandwidth 12MHz 1/f noise 30kHz corner
Harmonic Rejection Ratio @ 0.8GHz LO
3rd-order > 60dB (40 chips) 5th-order > 64dB (40 chips)
2nd, 4th, 6th > 62dB (20 chips)
36
Conclusion: A SDR Receiver Architecture
Robust to Out-of-Band Interference
• Only voltage gain @ BB after low-pass filtering – In-band IIP3 +3dBm & out-of-band IIP3 +18dBm
• 2-stage polyphase harmonic rejection technique – Robust: error = product of errors – Accurate multiphase clock – Minimum HR 60dB over 40 chips without
calibration / trimming / RF filters
Outline
• Introduction • Balun-LNA-Mixer (BLIXER) • Interferer robust SDR RX – analog part • Interferer robust SDR RX – digital part • Summary
The Digital approach:
Harmonic Rejection Exploiting Adaptive
Interference Cancellation
[Moseley, ISSCC 2009]
38
39
Harmonic Rejection RX: This work
ADC
ADC
ADC
ADC
x0
x45
x90
x135
2Gm
2Gm
3Gm
-+-+
-+-+
-+-+
-+-+
RF+-
Chip
8
8CLK+-
50Ω
50Ω
100Ω
To Digital Harmonic Rejection Algorithm
(Baseband processor)
40
The Basic Idea
Subtract interference (residual harmonic image responses)
from received signal.
• Need interference estimate signal.
-Interference
Estimate
Desired Signal+ Interference Desired Signal
d(n)
v(n)
e(n)
41
Adaptive Interference Cancelling (AIC)
• Adaptive “filter” aligns phase & amplitude. • Minimizes cross-correlation v(n) and e(n).
Digital“Filter”
-Interference
Estimate
Desired Signal+ Interference Desired Signal
LearningAlgorithmFilter Coefficients
w(n)
r(n)
v(n)
e(n)
y(n)
42
Two I/Q signals
ADC
ADC
ADC
ADC
x0
x45
x90
x135
2Gm
2Gm
3Gm
-+-
+
-+-
+
-+-
+
-+-
+
RF+-
Chip
8
8CLK+-
50Ω
50Ω
100Ω
r(n) = x0 + j·x90
IQ2(n) = x45 + j·x135
43
Interference estimate
r(n) IQ2 IQ’2 v(n)=r(n)-IQ’2Desired signal
3rd harmonicresponse
r(n) IQ2 IQ’2 v(n)=r(n)-IQ’2
5th harmonicresponse
r(n) IQ2 IQ’2 v(n)=r(n)-IQ’2
44
AIC Algorithm 1/5
RF Input
ADC
ADC
ADC
ADC
j
j
-45°
(.)*
w1* w2*
- -r(n)
v(n)
e(n)
LMSupdate
x0
x45
x90
x135
IQ1
IQ2
Adaptive Interference Canceller
To Rest ofBaseband Processing
Master Clock
ANALOG
FRONT
END
45
AIC Algorithm 2/5
RF Input
ADC
ADC
ADC
ADC
j
j
-45°
(.)*
w1* w2*
- -r(n)
v(n)
e(n)
LMSupdate
x0
x45
x90
x135
IQ1
IQ2
Adaptive Interference Canceller
To Rest ofBaseband Processing
Master Clock
ANALOG
FRONT
END
46
AIC Algorithm 3/5
RF Input
ADC
ADC
ADC
ADC
j
j
-45°
(.)*
w1* w2*
- -r(n)
v(n)
e(n)
LMSupdate
x0
x45
x90
x135
IQ1
IQ2
Adaptive Interference Canceller
To Rest ofBaseband Processing
Master Clock
ANALOG
FRONT
END
47
AIC Algorithm 4/5
RF Input
ADC
ADC
ADC
ADC
j
j
-45°
(.)*
w1* w2*
- -r(n)
v(n)
e(n)
LMSupdate
x0
x45
x90
x135
IQ1
IQ2
Adaptive Interference Canceller
To Rest ofBaseband Processing
Master Clock
ANALOG
FRONT
END
48
AIC Algorithm 5/5
RF Input
ADC
ADC
ADC
ADC
j
j
-45°
(.)*
w1* w2*
- -r(n)
v(n)
e(n)
LMSupdate
x0
x45
x90
x135
IQ1
IQ2
Adaptive Interference Canceller
To Rest ofBaseband Processing
Master Clock
ANALOG
FRONT
END
49
Demonstration
50
Demonstration
51
Demonstration
52
Demonstration
53
Demonstration
54
Comparison
This work Z. Ru ISSCC 2009 12.8
Rej. strongest >80 dB (1) >60 dB
Rej. other odd >36 dB >60 dB
Rej. even >64 dB >62 dB
Power frontend 45 mA @ 1.2 V (excl. ADCs)
50 mA @ 1.2 V (excl. ADCs)
Power DSP (100 Msps)
55
Adaptive Interference Cancellation: Conclusions
Dual-domain Harmonic Rejection Mixer (HRM) proposed: – Analog HRM + 4 ADCs + Digital AIC. – Strongest correlating harmonic image is removed – X-correlation -> independent of signal shape. – Stronger interferer -> more rejection
• Measurements: – First stage (analog) HR > 36 dB. – Dual domain HR3 or HR5 > 80 dB. – Limitation: even-order HR > 64 dB.
Outline
• Introduction • Balun-LNA-Mixer (BLIXER) • Interferer robust SDR RX – analog part • Interferer robust SDR RX – digital part • Summary
57
Summary
• BLIXER – Noise cancelling – no voltage gain @ RF
• Interferer robust RX – No voltage gain @ RF – Filter before voltage gain – HR: error of errors
58
Summary
• Digital Harmonic Rejection RX – Adaptively kills the biggest harmonic interferer
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