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EE304 Electronic Circuits - II Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore HOME ASSIGNMENT 1. For the differential amplifier circuit shown below in figure.Q1, let I=1 mA, V CC =5V, v CM = -2V, R C =3kΩ and β=100. Assume that the BJTs have v BE =0.7 V at i C =1 mA. Find the voltage at the emitters and at the outputs. 2. For the differential amplifier circuit shown below in figure.Q2 with an input of +1V and with I=1 mA, V CC = 5V, R C =3kΩ and β=100, find the voltages at the emitters and the collector voltages. Assume that the BJTs have v BE =0.7 V at i C =1 mA. Figure.Q1 Figure.Q2 3. For the BJT differential amplifier shown below in figure.Q3, find the value of the input differential signal, v id = v B1 – v B2 , that causes i E1 = 0.80I. Figure.Q3 4. When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 40 dB higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be in percent?

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Page 1: i = 0 - eeeforum - Homeeeeforum.weebly.com/uploads/1/0/2/5/10254481/ec304_qpa.pdfEE304 Electronic Circuits - II Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore

EE304 Electronic Circuits - II

Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore

HOME ASSIGNMENT

1. For the differential amplifier circuit shown below in figure.Q1, let I=1 mA, VCC=5V, vCM = -2V, RC=3kΩ

and β=100. Assume that the BJTs have vBE=0.7 V at iC=1 mA. Find the voltage at the emitters and at the

outputs.

2. For the differential amplifier circuit shown below in figure.Q2 with an input of +1V and with I=1 mA,

VCC = 5V, RC=3kΩ and β=100, find the voltages at the emitters and the collector voltages. Assume that the

BJTs have vBE=0.7 V at iC=1 mA.

Figure.Q1 Figure.Q2

3. For the BJT differential amplifier shown below in figure.Q3, find the value of the input differential signal,

vid = vB1 – vB2, that causes iE1 = 0.80I.

Figure.Q3

4. When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 40 dB

higher than when the output is taken single-endedly. If the only source of common-mode gain when the

output is taken differentially is the mismatch in collector resistances, what must this mismatch be in percent?

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EE304 Electronic Circuits - II

Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore

5. The differential amplifier shown below uses transistors with β=100. Evaluate the following:

a) The input differential resistance Rid.

b) The overall differential voltage gain vo/vsig (neglect the effect of ro)

c) The CMRR in dB.

Figure.Q5

6. For the circuit below determine an optimum value for Roffset to minimize offset and drift. Determine the

output offset voltage if Vos= 3mV and Ios = 100nA. Ri = 2kΩ, Rf = 40kΩ, Rload = 20kΩ.

7. Find the voltage gain, input impedance, and output voltage.

Figure.Q6 Figure.Q7

8. For the circuit below, find the voltage gain, input impedance, and output voltage. If slew rate is 2 volts per

microsecond, find fmax (power bandwidth) for a 10 volt peak output.

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EE304 Electronic Circuits - II

Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore

9. A 5 kHz square wave with 10 Vpp is applied to a practical integrator. Show the output waveform voltages.

Figure.Q8 Figure.Q9

10. A 1.0 kHz, 10 Vpp triangular wave is applied to a practical differentiator as shown in figure.Q10. Show the

output in relationship to the input.

11. A Miller integrator whose input and output voltages are initially zero and whose time constant is 1ms is

driven by the signal shown below. Sketch and label the output waveform that results. Also sketch and label

the output waveform, when fed with a string of pulses of 10 µs duration and 1 V amplitude rising from 0.

Figure.Q10 Figure.Q11

12. Design a circuit, using one ideal op-amp, whose output is vo = vI1 + 3vI2 – 2(vI3 + 3vI4).

13. Use two ideal op-amps and resistors to implement the summation function.

vo = v1 + 2v2 – 3v3 – 4v4

14. Determine the frequency of oscillation of the circuit below. Ri=10kΩ, Rf=15kΩ, Rd=8kΩ, R=20kΩ,

C=0.1uF

Figure.Q14

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EE304 Electronic Circuits - II

Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore

15. The figure below shows the loop gain of a feedback amplifier of an op amp.

(a) How much must the loop gain be reduced to just make the amplifier stable?

(b) Estimate the reduction in loop gain to make the amplifier stable with a 45o phase margin.

16. For the class-A amplifier shown, show that the maximum efficiency for a sinusoidal input signal 25%.

Clearly state assumptions you make. For example, “ignore saturation…”

17. A class A emitter follower, biased using the circuit shown in figure.Q17 uses VCC = 5V, R = RL = 1kΩ,

with all transistors (including Q3) identical. Assume VBE = 0.7 V, VCEsat = 0.3 V, and β to be very large. For

linear operation, what are the upper and lower limits of output voltage, and the corresponding inputs?

Figure.Q16 Figure.Q17

18. The output voltage of a three-terminal voltage regulator is 5 V @ 5 mA load, and 4.96 V @ 1.5 A load.

What is the regulator’s output resistance and load regulation?

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EE304 Electronic Circuits - II

Electrical & Electronics Engineering, Amrita Vishwa Vidhyapeetham, Coimbatore

19. What is vo in the following circuit if VREF= 2 V, R1 = 500Ω, and R2=200Ω?

20. What is the output voltage of the series regulator?

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