HARDWARE-IN-THE-LOOP EXAMPLES ANDASSESSMENT OF ACCURACY

OCTOBER 29, 2019 I A. BENIGNI

HIGH SPEED, SCALABLE, SYSTEM LEVEL, REAL-TIME SIMULATIONEnable high-speed, scalable, real-time simulation of power electronics based systems (Δt<100ns)

• Infinitely scalable

• Without manual partitioning

• Define and evaluate –using a FPGA platform– simulation methods based on Latency Insertion Method and on Latency Based Linear Multi-step Compound Method.

• Support multi-FPGA execution.

Code generation and open source access • Full code generation support from net list description

• Available at https://github.com/MatthewMilton/LBLMC-CodeGen

• Execution on Xilinx evaluation boards, custom hardwareand NI platforms

LATENCY-BASED LINEAR MULTI-STEP COMPOUND METHOD

3

𝑑𝑖#$

𝑑𝑡 = 𝑓(𝑣, 𝑖, 𝑥#$, 𝑢#$, 𝑡)

𝑑𝑣.$

𝑑𝑡 = 𝑓(𝑣, 𝑖, 𝑥.$, 𝑢.$, 𝑡)

)𝐼#$ 𝑘 + 1 = 𝑓(𝑣 𝑘 , 𝑖 𝑘 , 𝑥#$ 𝑘 , 𝑢#$ 𝑘 , 𝑘

3𝑉.$ 𝑘 + 1 = 𝑓(𝑣 𝑘 , 𝑖 𝑘 , 𝑥.$ 𝑘 , 𝑢.$ 𝑘 , 𝑘

)𝐺𝑥 𝑘 + 1 = 𝑏(𝑣 𝑘 , 𝑖 𝑘 , 𝐼$ 𝑘 , 𝑉$ 𝑘 , 𝑘

Nonlinear components

Nonlinear components

explicitly integrated

Linear part of the system implicitly

integrated

LATENCY INSERTION METHOD FOR POWER ELECTRONICS

4

An example

TEST RESULTS

Reference Solver

Three Phase Inverter

Single Bus System

Dual Bus System

LB-LMCFloating Pt. C++ (%)

85.97e-6 0.0087 0.0141

EMTP (%) 1.0034 0.6545 0.5221

LIM Floating Pt. C++ (%)

676.07e-6 0.0011 452.72e-6

EMTP (%) 0.0162 0.01402 0.01077

Overall 2-Norm Percent Error

LB-LMC Δt = 50nsLIM Δt = 40ns

SCALABILITY ANALYSISMODEL AND EVALUATION RESULTS

LB-LMC LIM

6

NODAL DECOMPOSITION

𝐼# = 789:

;

𝛼#,8𝐼8 + 7=9:

>

𝛽#,=𝑉=

MULTI-FPGA IMPLEMENTATION

TEST MODEL

TEST RESULTS

Undecomposed vs. A

Undecomposed vs. B

OverallError % 2.563e-04 3.237e-04

GreatestError % 0.628e-03 0.370e-03

Undecomposed

(FPGA 1)

Decomposed

(FPGA 1)

Decomposed

(FPGA 1/2)dt 100ns real-time

DSP 1114 (133%)

1178(140%)

552/552(66%/66%)

LUT 46239 (22%)

51483 (25%)

17473/16308

(9%/8%)

FF 6974 (1%)

10240(2%)

3117/2876(1%/1%)

HIL FOR PROTECTION TESTING

11

COTS RT FPGA-based Solver: 1 µS → about 9 samples/periodLB-LMC RT FPGA-based Solver : 50 nS → about 180 samples/period

About 50 meters of Cabling

LG fault circuit forms an underdamped LC Circuit based on cable inductance and parasitic capacitance.

HIL FOR PROTECTION TESTING

12

+

+(a)

(c)

botL

(b)

av

-

-

topLtopR

botR -

+

bv-+

cv-+ +

iCV

-+0S =

-

botgV

topgV topg

i

botgi

topi

boti

+

-

C bR

1S =

iCV

NSM

1NSM + 1NSM +1NSM +

2NSM 2NSM 2NSM

iSM iSM

NSM

iSM

NSM

topgR

topgV

topgi

botgibotgV

RL 1 2

3 4

56

7

C

MMC#1

botgR

MMC#2

MMC#n

MMC MODEL

MMC MODEL - VALIDATION

HIL INTERFACE FOR SYSTEM TESTING

HIL INTERFACE FOR SYSTEM TESTING

Long parallel

BUS

OPAL OP5607 Multi CPU unit

PCIe

HOST PCRT LAB CONSOLE

GGOV1

Shaft

SynchronousMachine #1

SynchronousMachine #2

IEEEExciter

Tg

w

w

T1

T2

Tabs Vf

Vf

Vd,Vq

Va,Vb,Vc

Vx,Vy,Vz

Va,Vb,Vc

Vx,Vy,Vz

FPGA VC707

SFP -CH#1

SFP -CH#2

FPGA kit#2 (Ultrascale)FPGA kit#1 (Ultrascale)

MMC

Control

MMC

Control

Gates signals

Gates signals

DCDC

DCDC

Load

DCDC

DCDC

Load

DCDC

DCDC

Load

DCDC

gates

I1,I2,I3

gates

I1,I2,I3

Control

V?,I?

gates

PWMgates

I1,I2,I3

PWMgates

I1,I2,I3

gates

I1,I2,I3

gates

I1,I2,I3

Vdc,??

CLOCK GENERATOR FPGAs Cluster

CTRL Zone#2

FMCFM

C

Iref_4

Iref_3

Vo2

UDP/IP

PCM#1

PCM#2

PCM#3

PCM#4 PCM#6

PCM#5

PCM?

Vo1,Io1 Vo2,Io2 Vo3,Io3

V-CtrlZone1

V-CtrlZone3

Current Control Iref_1

Iref_2

Vo1

Current Control

Current Control

Current Control

Iref_5

Iref_6

Vin_up

Vin_low

Vo3

Vin_up

Vin_low

Vo1

Vo2

Vo3

Io1

Io2

Io3

VstoreIstore

Iin1

Iin2

Iin3

Iin5

Iin6

Iin4

Vstg

Istg

PGM MODEL

Zones On/Off

LOG

uni

t

Va

Vb

Vc

Vx

Vy

Vz

Ia

Ib

Ic

Ix

Iy

Iz

w

Tg

Tabs

AOs

AOs

Kintex-7Conversion

Aurora 32bit- to Aurora64bit FM

C-Tr

ansc

eive

rs a

dapt

er(A

uror

a64b

it)

SFP

chan

nels

Auro

ra

com

mun

icat

ion

prot

ocol

.

+

+(a)

(c)

botL

(b)

av

-

-

topLtopR

botR -

+

bv-

+

cv-

+ +iC

V

-+0=S

-

botgV

topgV topg

i

botgi

topi

boti

+

-

C bR

1=S

iCV

NSM

1+NSM 1+NSM1+NSM

2NSM 2NSM 2NSM

iSM iSM

NSM

iSM

NSM

Dual Wound Machine

Long parallel

BUS

OPAL OP5607 Multi CPU unit

PCIe

HOST PCRT LAB CONSOLE

GGOV1

Shaft

SynchronousMachine #1

SynchronousMachine #2

IEEEExciter

Tg

w

w

T1

T2

Tabs Vf

Vf

Vd,Vq

Va,Vb,Vc

Vx,Vy,Vz

Va,Vb,Vc

Vx,Vy,Vz

FPGA VC707

SFP -CH#1

SFP -CH#2

FPGA kit#2 (Ultrascale)FPGA kit#1 (Ultrascale)

MMC

Control

MMC

Control

Gates signals

Gates signals

DCDC

DCDC

Load

DCDC

DCDC

Load

DCDC

DCDC

Load

DCDC

gates

I1,I2,I3

gates

I1,I2,I3

Control

V?,I?

gates

PWMgates

I1,I2,I3

PWMgates

I1,I2,I3

gates

I1,I2,I3

gates

I1,I2,I3

Vdc,??

CLOCK GENERATOR FPGAs Cluster

CTRL Zone#2

FMCFM

C

Iref_4

Iref_3

Vo2

UDP/IP

PCM#1

PCM#2

PCM#3

PCM#4 PCM#6

PCM#5

PCM?

Vo1,Io1 Vo2,Io2 Vo3,Io3

V-CtrlZone1

V-CtrlZone3

Current Control Iref_1

Iref_2

Vo1

Current Control

Current Control

Current Control

Iref_5

Iref_6

Vin_up

Vin_low

Vo3

Vin_up

Vin_low

Vo1

Vo2

Vo3

Io1

Io2

Io3

VstoreIstore

Iin1

Iin2

Iin3

Iin5

Iin6

Iin4

Vstg

Istg

PGM MODEL

Zones On/Off

LOG

uni

t

Va

Vb

Vc

Vx

Vy

Vz

Ia

Ib

Ic

Ix

Iy

Iz

w

Tg

Tabs

AOs

AOs

Kintex-7Conversion

Aurora 32bit- to Aurora64bit FM

C-Tr

ansc

eive

rs a

dapt

er(A

uror

a64b

it)

SFP

chan

nels

Auro

ra

com

mun

icat

ion

prot

ocol

.

+

+(a)

(c)

botL

(b)

av

-

-

topLtopR

botR -

+

bv-

+

cv-

+ +iC

V

-+0=S

-

botgV

topgV topg

i

botgi

topi

boti

+

-

C bR

1=S

iCV

NSM

1+NSM 1+NSM1+NSM

2NSM 2NSM 2NSM

iSM iSM

NSM

iSM

NSM

Dual Wound Machine

REAL TIME CO-SIMULATION

Opal-RtOP5607

Kintex-7

Fiber optic cable

Fiber optics cable

Clock Generator (Virtex-7)

VirtexUltrascale+

dt = 25µs

dt = 50ns

dt = 50ns200MHz

SMA cables

SMA cables

FMC Parallel Bus

FMC Parallel Bus

REAL TIME CO-SIMULATION EXAMPLEGv(s)

Gi(s)

VdcC

MV DC Bus

+ -

Vdc

C

Gi(s)

In Z

one

DC B

us

Zonal Loads

*DCV

K1(s)

K2(s)COMM

LINK

COMMLINK

COMMLINK

System Wide Control

PCM

PCM

MV DC Bus

REAL TIME CO-SIMULATION EXAMPLE

LIVING LAB ENERGY CAMPUS

Seite 20

Project highlights

² Combined heat and power plant (CHP) with H2 co-firing from photovoltaics and wind power

² Different photovoltaics systems (BIPV, open field, Agro PV)

² Lithium-ion batteries as UPS, storage and peak shaving units

² Hydrogen infrastructure with electrolyser, storages, and fuel cell

² HPC waste heat usage for district heating (low temperature network)

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² Engagement of consumers as „prosumers“

Budget (Mio. €): 36.5 (FZJ) | 3 (KIT) duration/personel: 2018 – 2022 / 35 FTE

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Sensor values

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…

Local controller

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A NEW HARDWARE IN THE LOOP LABORATORY FOR ENERGY SYSTEMS