Analog Verification, An Introduction

AnalogVerification

KenKundert

Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

DesignsTheyAreAChangin

Size

AlgorithmicArchitectures

Modes&Settings

InMultipleDimensions!

BobDylan,1964

TheComplexityofDesignisGrowingRapidly

>100Ktransistors

architecturesAutocalibrationAdaptivefilteringEtc.

PowermodesDigitaltrimmingMultiplestandardsEtc.

19902000

2010


FunctionalErrors Functionalerrorsareoftenverysimpleerrors

Invertedsignals Corruptlogic Flippedbusses Unaccountedfordependencies(chicken/eggproblem) Communicationerrors

Butaregenerallycatastrophic

Design


InRecentVerificationEfforts Wefound

swappedinputs logicerrorthatprecludedsleepmode bussesswapped dependencyloop(chicken&eggproblem) invertedbiascurrent wiresswapped invertedinput swappedreset&resetbar logiclinescrossingsupplydomainsw/olevelshifters incorrectRTL undriven logicsignalinanalogtoplevel errorsinregistermap manyspecerrors Andmore


5TheThreeBasicIssues

Detailedverificationonlyperformedatblocklevel Allrequiredsignalsareassumedtobepresent Assumptionsoninterblockdependenciesneververified

Verificationonmostmodesneverperformed Onlytypicalorworstcasemodes Anycontrollogicthatsupportsuntestedmodecouldcontainhiddenerror

Noanalog digitalcoverification


TransistorLevelVerification

Tooexpensiveforfunctionalverification 10Ktransistors,30Kcycles,250modes Oneweekforonemodewithtimingsimulator

Neednightlyregressiontests 10K speedupneeded

Chiplevelrequires 100K1M speedups


WhatsNeeded

Systematicapproachtoverifyingdesign&specification

Confidencethatallflawshavebeenfound Moreverification,earlierindesignflow

Errorsareeasiertofix&lessdisruptive Helpwithperformanceverification Accuratemodelofmixedsignalsection


TheAnswer

Functionalverificationwith Modelbasedverification

DramaticallyacceleratesthesimulationMovesitearlierindesigncycle

ExhaustiveregressiontestingCheckeverymodeandeverysettingAutomatedpass/failtests(selfcheckingtests)

CreationofaverifiedsignoffqualitytoplevelmodelOftenmustbepureVerilog orVHDL


9ThisisAnalogVerification

Exhaustiveregressiontesting Traceabletotransistorlevel Verifiesbothmodelsandcircuits

Testbenchesverifybehaviorofmodels Methodologyassuresmodelsareconsistentwithcircuit

DrivenbyanalogverificationengineerWe can now imagine a future where we are surprised when an analog chip does not function the first time.


Conclusions

Complexsystemdesignrequiresarigoroussystemverificationmethodology

Chipdesignandanalogimplementationneedstobelinkedforverification

AVcanbedonetoday ModelingandRegressionTesting

Thebiggerthesystem,themorebenefitwillbederivedfromusingAV


DesignersGuideConsulting Adoptinganalogverificationisadifficultprocess,filledwithpotentialpitfalls

Wecanhelpguideyouthroughtheprocess Teachclasses Trainingyourverificationengineers Guideverificationplanning Consultondifficultmodels&tests

Howtocreateveryfastanalogmodelsinverilog Howtoovercomeperformanceissues

ProvideAVservices


References H.Chang&K.Kundert.VerificationofComplex

AnalogandRFICDesigns.TheProceedingsoftheIEEE.March2007.

K.Kundert&H.Chang.VerificationofComplexAnalogIntegratedCircuits.CICC06.

K.Kundert&O.Zinke.TheDesignersGuidetoVerilogAMS.2004.

K.Kundert.Principlesoftopdownmixedsignaldesign.www.designersguide.org/Design.

A.Meyer.PrinciplesofFunctionalVerification.2003. AnalogVerificationNewsletter.www.designersguide.com/newsletters


ForMoreInformation

www.designersguide.com


Analog VerificationDesigns They Are A-ChanginFunctional ErrorsIn Recent Verification EffortsThe Three Basic IssuesTransistor-Level VerificationWhats NeededThe AnswerThis is Analog Verification ConclusionsDesigners Guide ConsultingReferencesFor More Information

Analog Verification, An Introduction

Documents

Transcript of Analog Verification, An Introduction