Sigma-Delta Analog to Digital Converters

Sigma-Delta Analog to Digital Converters(Σ∆ADCs)

Satish Patil

Dept. of Electrical EngineeringIndian Institute of Techology, Bombay

(IIT Bombay) Sigma-Delta ADC 1 / 29

Outline

Basic principle

Effect of oversampling and noise shaping

1st and 2nd -order modulator (MOD1 and MOD2)

Effect of Noise shaping on total noise

Issues in modulator design

Discrete and Continuous time realization

Inherent anti-aliasing property of CT modulators

Effect of Quantizer bits

Maximum stable amplitude

Loop filter architectures

Multi-stage (Cascaded) Σ∆ modulators

Design example


Block diagram of Σ∆ADC

General bolck diagram

2 major parts- Modulator and Decimator


Basic principle of Sigma-Delta (Σ∆) modulator

Oversampling + Noise shaping

Oversampling: sampling input signal with frequency multiples ofNyquist rate - Over Sampling Ratio (OSR)

Noise shaping: selecting proper loop transfer function such thatspectral density of inband noise can be reduced

Key features: coarse quantization, filtering,feedback

Quantization is often quite coarse (1 bit!), but the effective resolutioncan still be as high as 10-22 bits.


Effect of oversampling and noise shaping

0Reference: Industrial Sigma Delta Convertors Overview, Analog Devices Webcast Technical Seminar Series


1st-order modulator (MOD1)

Vo(z) = Ui (z).z−1 + En(z).(1− z−1)

STF = z−1,NTF = (1− z−1)

out of band gain (gain at z = −1) or ||H||∞ = 2

|NTF (e−jω)| = |1− e−jω| = |ejω2 − e−

jω2 | = 2sin(ω2 ) at low

frequencies(approx.) |NTF (e−jω)| ≈ ω


2nd -order modulator (MOD2)

Vo(z) = Ui (z).z−2 + En(z).(1− z−1)2

STF = z−2,NTF = (1− z−1)2

||H||∞ = 4

|NTF (e−jω)| = |1− e−jω|2 = |ejω2 − e−

jω2 |2 = 4sin2(ω2 ) at low

frequencies(approx.) |NTF (e−jω)| ≈ ω2


Noise performance

Inband Quantization noise power = ∆2

12π

∫ πOSR

0 |NTF (jω)|2dωFor 1st order SDM,


12π

∫ πOSR

0 ω2dω = ∆2

12π13

π3

OSR3

For every doubling in OSR, noise power decreases by factor of 8 henceincrease in effective no. of bits (ENOB)≈ 1.5bits

For 2nd order SDM,


12π

∫ πOSR

0 ω4dω = ∆2

12π15

π5

OSR5

Increase in ENOB for every doubling in OSR≈ 2.5bits1

1Reference: online video lectures of VLSI Data conversion circuits(EE658), IIT Madras


Noise shaping

Figure: Noise shaping vs order Figure: zoomed portion

Out of Band gain increases with very rapidly with increase inmodulator order

Better inband, Worst out of band noise performance!


Effect of Noise shaping on total noise

Total Q. noise power is calculated by ∆2

12π

∫ π0 |NTF (jω)|2dω

MOD1: with only oversampling, STF = 1, NTF = 1, total noisepower is ∆2

12with oversampling & noise shaping, STF = 1,NTF = (1− z−1), total noise power is ∆2

12π2π = 2 ∆2

12

MOD2: with only oversampling, STF = 1, NTF = 1, total noisepower is ∆2

12with oversampling & noise shaping, STF = 1,NTF = (1− z−1)2, total noise power is 6 ∆2

12

Noise shaping results in increase in total Q.noise!

this phenomenon even gets worse for higher order modulators

Total noise can also be derived using Parseval’s theorem:∆2

12π

∑k

h2(k) = ∆2

12π

∫ π0 |NTF (jω)|2dω


Issues in modulator design

SNR for oversampled noise shaping converter isSNRdB = 6.02B + 1.76 + 10log( 2L+1

π2L ) + (2L + 1)log10(OSR) where,B=quantizer bitsL=order of modulatorOSR=oversampling ratio

Ways to improve SNR

i. increasing loop orderii. increasing OSRiii. increasing quantizer resolution

Higher order modulators are highly unstable. This issue can beaddressed by using multi stage noise shaping (MASH) architecture.

quantizer overloading issue can be checked by MSA simulation


Block diagram of CT and DT Σ∆ADC

Contineous-time SDM provides inherent anti-aliasing

performance of CT is highly volatile to shape of pulse used for DAC2

2source: Jose M de la Rosa. Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art

survey. Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(1):121, 2011


SNR vs OSR

Figure: SNR vs oversampling ratio for different modulator orders3

3All MATLAB simulations are carried using R.Schreier,Σ∆ Toolbox, online available :

http://www.mathworks.com/matlabcentral/fileexchange19


Inherent anti-aliasing property of CT modulators

Figure: 1st order modulator with Anti-aliasing filter

Figure: 1st order continuous time modulator


Inherent anti-aliasing property of CT modulators...

Figure: CT MOD1 after block adjustment


Inherent Anti-Aliasing property of CT modulators...

Figure: Frequency response of MOD1 CT modulators

unlike DT Σ∆ modulator, response to ∆ and 1 + ∆ is not same.

For higher orders, alias rejection response of CTΣ∆ modulators getsbetter and better!


Effect of Quantizer bits

nLev SNR(in dB) MSA/VRef

2 135 0.703

4 141.8 0.834

8 149.3 0.874

16 157.4 0.889

32 163.4 0.894

64 166.4 0.898

Results shown above are for order=3, OSR=256, N=8192

Risbo’s method is used for calculation of MSA.


Effect of Quantizer bits (order=2, OSR=64)

Figure: Time domain simulations for nlev=2,4,8 and 16


Maximum Stable Amplitude(MSA)

Idea: apply slowly increasing ramp input over sufficiently large points(1 Mega points) and find when y crosses threshold point.

Figure: input ramp and observed output of Σ∆ modulator(IIT Bombay) Sigma-Delta ADC 19 / 29

MSA cont’d

Figure: time domain output of waveform used to calculate MSA

MSA: 90% of input where y blows away (in this case, y blows awayfor input=0.97 of fullscale)


Loop filter architectures

Feedback topologiesI Cascade of Integrators Feedback form (CIFB)I Cascade of Resonators Feed-forward form (CRFB)

lower power consumption at expense of higher distortion andcomplexity of multiple feedback DACs

Feed-forward topologiesI Cascade of Integrators Feedback form (CIFF)I Cascade of Resonators Feed-forward form (CRFF)

Low signal distortion.only one DAC is required in feedback loop but extra amplifier is neededto accurately sum up input and integrator output4

4J. Silva, U. Moon, J. Steensgaard, and G. Temes. Wideband lowdistortion delta-sigma ADC topology,

Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.


Loop filter architectures...

Figure: CIFB Figure: CRFB

Figure: CIFF Figure: CRFF

Figure: CIFB, CRFB, CIFF, CRFF topologies


Multi-stage (Cascaded) Σ∆ modulators

Higher-order noise shaping can be achieved by cascading first-ordermodulators

The first modulator converts theanalog input signal

Each subsequent modulatorconverts the quantization errorfrom the previous modulator

The quantization noises aredigitally cancelled

This gives a higher order ofnoise shaping, without causinginstability


Multi-stage (Cascaded) Σ∆ modulators...

y1(z) = x1(z)z−1 + e1(z)(1− z−1) andy2(z) = e1(z)z−1 + e2(z)(1− z−1)

so output y(z) = y1(z)z−1 + y2(z)(1− z−1)⇒ y(z) = x(z)z−2 + e2(z)(1− z−1)2

Advantage: 2nd order noise shaping is achieved though 1st order loopis implemented

However, cancellation of e1 is not perfect since the analog transferfunctions are not ideal


Design Example

Design specifications:I input frequency=500HzI SNR > 100dB (>16 bit resolution)I use 1-bit quantizer

we design modulator for 17 bit resolution. 1st and 2ndorder loopfilters improves SNR by 9dB (1.5bits) and 15dB (2.5bits) per octave.

increment needed in resolution=16 bits, henceI If L=1, then OSR> 2

161.5 ⇒ OSR = 2048

I If L=2, then OSR> 2162.5 ⇒ OSR = 256

since case of 2048 OSR is difficult to implement we go for OSR=256,order=2. NTF obtained using these specs:TF = z2−2z+1

z2−1.225z+0.441

for 2nd order modulator H(−1) = 2, we select ||H||∞ = 1.5 whichensures stability and avoid quantizer overload


Design Example...


Design Example...

SNR achieved from simulations: 100.9dB

MSA obtained by Risbo’s method: 90% of Vref

for CRFB topology coefficients obtained are as:

a : 0.2163 0.5585g : 5.0199e-05b : 0.2163 0.5585 1.0000c : 1 1


References I

Jose M de la Rosa.

Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art survey.Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(1):1–21, 2011.

Shanthi Pavan and Prabu Sankar.

Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique.Solid-State Circuits, IEEE Journal of, 45(7):1365–1379, 2010.

Youngcheol Chae and Gunhee Han.

Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator.Solid-State Circuits, IEEE Journal of, 44(2):458–472, 2009.

Chia-Ling Chang and Jieh-Tsorng Wu.

A 1-v 100-db dynamic range 24.4-khz bandwidth delta-sigma modulator.In Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, pages 813–816. IEEE, 2013.

Dushyant Juneja, Sougata Kar, Procheta Chatterjee, and Siddhartha Sen.

Design of delta sigma modulators for integrated sensor applications.Control Theory and Informatics, 3(2):25–34, 2013.

J Silva, U Moon, J Steensgaard, and GC Temes.

Wideband low-distortion delta-sigma adc topology.Electronics Letters, 37(12):737–738, 2001.

Fridolin Michel and Michiel SJ Steyaert.

A 250 mv 7.5 µw 61 db sndr sc δσ modulator using near-threshold-voltage-biased inverter amplifiers in 130 nm cmos.Solid-State Circuits, IEEE Journal of, 47(3):709–721, 2012.


References II

Younghyun Yoon, Hyungdong Roh, Hyuntae Lee, and Jeongjin Roh.

A 0.6-v 540-nw delta-sigma modulator for biomedical sensors.Analog Integrated Circuits and Signal Processing, pages 1–5, 2013.

Hao Luo, Yan Han, Ray CC Cheung, Xiaopeng Liu, and Tianlin Cao.

A 0.8-v 230-w 98-db dr inverter-based modulator for audio applications.2013.


Sigma-Delta Analog to Digital Converters

Engineering

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