3M lkkb. rRANSAC'l IONS O N F,LE.,C'rRON 1)t~VICFS. V O L 40. N O . 2 . F t B R U A R Y 1993

Aging Analysis of nMOS of a 1.3-pm Partially Depleted SIMOX SO1 Technology

Comparison with a 1.3-pm Bulk Technology

Gilles Reimbold and Andre-Jacques Auberton-Herve

Abstract-Hot carrier degradation of nMOS of a 1.3-pm par- tially depleted rad-hard SO1 CMOS technology is analyzed in detail. The relative importances of the maximum electric field, the localization of the trapped charges, and the LDD structure are pointed out through two-dimensional simulations and sys- tematic comparisons with a 1.3-pm CMOS BULK technology. It is shown that the higher degradation rate of the SO1 tech- nology logically results from the contradictory constraints be- tween rad-hardness (low-temperature process) and hot carrier resistance requirements. An annealing scheme comparable to the bulk one would lead to similar degradations.

I . INTRODUCTION OT ELECTRON reliability of MOS transistors is a H key problem for the long-term stability of modern

VLSI. Several results have been published in the litera- ture comparing electric fields and aging of SO1 transis- tors.

Because of potential advantages of lower doping, lower electric field through lower Vu\3,, and current flowing far- ther from the gate of the device. fully depleted (FD) tran- sistors have been shown to exhibit lower degradation than partially depleted (PD) transistors [ 11. This has been con- firmed by measurements made on the same transistor using the back electrode to be in the FD (VGhklck = 0 V ) or in the PD ( VGh;,ck = -20 V ) mode. However rather than two technologies, the author compares two modes of opera- tion of a single device. The results could then only hold for FD and PD transistors with the same silicon layer thickness. It seems difficult to conclude that FD transis- tors of a self-consistently optimized technology would be more resistant than PD transistors of a self-consistently optimized one. This is argued by the strong electric field dependence on the silicon-film thickness. The electric field and the ionization rate increase when the silicon thickness decreases in the case of fully depleted devices [21-[51.

Manuscript received March 23. 1992: revised J u l ) 24. 1092. The revie\*

The authors are with LETI-MSC. C E N G B P 85X. F38041 Clrenoble-

IEEE Log Number 9204315.

of this paper was arranged by Associate Editor Y . Nish i .

Cedex, France.

Other authors have recently compared thin-film, 0.5-pm length process, SO1 technology, with 0.5-pm bulk technology [6]. They found a higher electric field and a higher ionization rate in the case of SO1 devices, leading to a higher device degradation. As in the previous case, these results hold only if they correspond to the self-con- sistently optimized technologies.

In this paper we present and analyze results of hot car- rier reliability of a low-temperature 1.3-pm partially de- pleted SOI-SIMOX technology. This technology has been carefully optimized for rad-hard applications. All this work will refer to nMOS devices. These results and the analysis are compared to corresponding results obtained on an industrial 1.3-pm BULK CMOS process. SUPREM 4 and PISCES simulations are systematically performed in order to analyze our results.

A short description of the technology will be given in Section 11. In order to better evaluate potential differences between SO1 and BULK transistors, Section I11 will com- pare simulations of electric fields of SO1 and BULK tran- sistors of a similar process. After having presented typical aging results in Section IV, analysis of electric fields and ionization currents will be presented in Section V. Section VI will show how to localize the trapped charges and how to quantify their value while Section VI1 will analyze the relationship between trapped charges and LDD doping. Conclusions and perspectives will be presented in Section VIII. We shall show that all our results can be clearly explained and that they result from the choices made for our process. Other choices would have led to completely different results. It emphasizes that great care must be taken in comparing different results.

11. MATE R I A L A N D DEvick FABRICATION

The SIMOX wafers were fabricated by high-current implantation of oxygen (1.8 x 10" cmp2, 200 keV, 600°C) and annealing above 1300°C in argon ambient. The devices are LOCOS-isolated n-channel MOSFET's with optimized LDD configuration (Np = 1 X 1OI3 cm-') to minimire the ionization rate [7]. The basic channel

1

365 REIMBOLD A N D A I J B E R I O i C H E R V ~ A G I N G A N A [ - Y S I S O F nMOS SO1 TECHNOLOGY

length is 1 pm, and the thicknesses of the gate oxide, bur- ied oxide, and Si film are 24, 400, and 150 nm, respec- tively. The average doping level N,, = IO" cm-j corre- sponds to the limiting edge of full depletion. Maximum process temperature after poly etching is 900°C. Circuit performance has been reported in 181. These devices will be called HSOI.

These SOI-SIMOX transistors have been compared with nMOS of an industrial 1.3-pm CMOS technology, with typical channel length of 1 pm, oxide thickness of 23 nm, and LDD N = 3 x 10'j cm-'. Maximum process tem- perature after poly etching is 1000°C. These devices will be called HCMOS.

111. SIMULATION OF SO1 A N D BULK nMOS W I T H A

SIMILAR PROCESS In order to investigate if SO1 transistors present original

behavior towards aging characteristics, we have investi- gated theoretically two kinds of transistors: 1 ) a SO1 tran- sistor and 2) a BULK transistor processed with the same CMOS technological process. There are two differences between these two kinds of transistors. The BULK device obviously has no buried oxide and it has its channel dop- ing implantation adjusted to have the same surface doping profile as for the SO1 transistor and the same threshold voltage.

The process simulated in this study corresponds to a high-temperature process, very similar to the HCMOS process.

Comparisons of total electric field along the channel are presented in Fig. 1 . Simulation conditions correspond to maximum ionization condition at V, = 5 V . The maxi- mum electric field appears to be slightly lower in the case of the SO1 transistor. One of the reasons is the spreading of the equipotential lines in the buried oxide. As a con- sequence, the ionization current appears to be slightly lower in the case of SO1 transistor as can be confirmed by Figs. 2 and 3 . The maximum ionization is farther from the interface in the case of the SO1 transistor and situated more under the gate. All these points would indicate a lower degradation in the case of the SO1 transistor. The conclusion of this study is that no particular comportment seems to be associated with the SO1 transistors as long as bias conditions remain far from the breakdown voltage. All the aging characteristics must be explained by doping profiles, process temperature. and the quality of the ma- terial.

Iv. A G I N G IN 'THE TWO IV15TIGATED TE.CHNC)LOGIES

Typical aging characteristics of the transistors of the two technologies described in Section I1 are given Fig. 4 . The stress conditions are VG = 2.5 V and V, = 6 V. Though it meets the lifetime criteria, the HSOI transistor presents a lifetime three to four decades lower than the HCMOS transistor. The HCMOS transistor exhibits a very large tolerance to hot-carrier effects. We are going to ex-

oistance (Microns)

Fig. I . Simulation of electric tield for SO1 and BULK transistors with an identical proccss. V(, = 2 . 5 V . V,, = 5 V. L,; = 1.3 hm. Localization = 300 A trom interfacc

1

U .

U ' m a 4 -

c: = - at. , I , , , , ' , , , , I , , , , A '3.53 0.60 0.70 0.80 0.90

list a x e (Microns)

Fig. 2 . Ionization rate near the drain for BULK transistor. Unit: pairs '

cni ' . s ' . Incrcment: 5 x lo2'. L,, = 1 . 3 Fni. v~; = 2.5 V . v,, = 5 V .

3 O - r - ar

cc3 0 d- 0 ' 10 '2-

d . - N -

O L , , , , I , , , , I , , I , I , , , , A C.50 0.60 0.70 0.80 0.90

Disr-ance (Microns)

. s I . Increment: s x 1 0 ~ ' . L( , = I .3 in. v,; = 2.5 V . vl1 = 5 V . Fig. 3. Ioniration rate near the drain lor SO1 transistor. Unit. pairs ' cm '

,01 L i o D 1 o 1 i o * 10'10' 1 0 ' 1 0 ~ ~ o ' ~ 0 8 ~ o p i o L o

Stress time ( s )

Fig. 4. Typical aging characteristics of HSOI and HCMOS transistors. V(, = 2.5 V . V I , = 6 V

366 IEEE TRANSACTIONS O N ELECTRON DEVICES. V O L 40. NO. 2. FFBRlJARY 1991

plain this discrepancy in the following sections and show how it results from the choices of the process.

Gate oxide quality has been carefully evaluated on ca- pacitors. The intrinsic quality of HSOI gate oxide has been found to be similar to that of the intrinsic HCMOS gate oxide [9]. This assures no potential increase of hot carrier susceptibility of HSOI transistors because of gate oxide quality.

The interface quality of the back interface is of prime importance not only in terms of time zero quality (since interface-state density and fixed oxide-charge density arc able to alter leakage currents) but also for long-term re- liability. In spite of continuous improvement of the ma- terial. the buried oxide has been shown to remain very susceptible to trapping of energetic carriers. The exis- tence of high electron trap densities has been reported [ I O ] , [ I 11. Low-field charge injection has shown that damage from electron injection can be significant for elec- tric fields as low as 2 MV/cm [12]. Stressing the back interface under hot carrier conditions has shown very high susceptibility to the trapping [ 131. High densities of elec- trons can be trapped, and over a much larger part of the channel ( ~ 0 . 5 pm) than at the front interface (= 0.15 pm) for the usual conditions.

This trapping can significantly alter front characteris- tics in the case of coupled interfaces of fully depleted de- vices [6], [ 141-[ 161. However, we have verified that this mechanism does not lead to significant front parameter degradation on our partially depleted nMOS HSOI tran- sistors.

v. ELECTRIC FIELD A N D IONIZATION CURRENT Fig. 5 shows electric field simulations for both HSOI

and HCMOS transistors. The bias conditions correspond to maximum ionization conditions for VI, = 5 V. The electric field is much higher in the case of the HSOI tran- sistor. Complementary simulations have shown that this difference corresponds to a 1.2-V difference in Vn. The electric field at 3.8 V for the HSOI transistor is equivalent to the electric field at 5 V for the HCMOS transistor. The higher electric field of the HSOI transistors is explained by a lower temperature of the process which induces a steeper LDD profile and a higher doping level of the chan- nel, which still contributes to accentuate the LDD profile because of the compensation of the N and P impurities.

Ionization is directly related to the electric field. The ionization rate (the ratio of bulk current over drain cur- rent) for VG = V,/2 is plotted in Fig. 6. In the case of HSOI transistors this current has been measured on spe- cial devices allowing a lateral access to the transistor body. Measuring the hole current tends to bias the body of the HSOI transistor to nearly 0 V and so to modify the potential distribution. However. complementary simula- tions have been performed on the HSOI transistors with- out and with an extra electrode to bias the body at 0 V. They have shown that the maximum electric field is very similar in these two cases. So IB/ID measurements on

Distdnce (MLcronsi

Fig. 5 . Comparison of electric field for HSOI and HCMOS transiqors. $imulation: L,; = I .3 pm. V( , = 2 . 5 V . k'!) = 5 V . Localization = 300 .A from interface.

10-6' ' ' 1 2 . 5 3,s 4.5 5 , s 6,s

VD (VI

Fig. 6. Ionization rate versus drain voltage. Measurement at V ( , ( I , , , , , , ) . HSOI: L,, = 1.4 pin, HCMOS: L,, = 1.25 pm.

HSOI transistors with lateral access must be representa- tive of a real transistor case. The ionization rate appears to be around six times higher for the HSOI transistor com- pared to the BULK transistor. This corresponds to around 1 V on the applied voltage, which is consistent with the 1.2-V difference obtained in simulations.

If we apply the classical law derived from bulk devices [ 171 to SO1 transistors

r being the lifetime of the device and m generally between 2.5 and 3 for our technologies, the difference in the ion- ization levels corresponds to a potential lifetime differ- ence of a factor between 100 and 200. Potential means that we exclude notions such as technology quality differ- ences and trapping mechanism differences. Compared to the effective three-to-four decades lifetime difference be- tween the two devices, there is still a discrepancy to ex- plain. We are going to explain partially this discrepancy through charge trapping analysis.

VI. CHARGE TRAPPING ANALYSIS

In this section we are going to show how to localize and estimate the trapping for our stress conditions. Fig. 7 shows a typical I f j ( V G ) curve before and after stress for an HSOI transistor. The shift is in this case 10% of linear current which is equivalent to I O % of G,,, and 5 mV on V,. The main point to notice is that we can reach a very

REIMBOLD A N D A U B b R T O N - H E R V C . AGING ANALYSIS OF nMOS SO1 T E C H N O L O G Y 367

6 - w .

9 5 :

4 -

3 -

2 -

~6

f m 4

.- 5

E 3

2

1

0 0 1 2 3 4 5

VG (v) Fig. 7 . Typical shift of the / />( V(,) curve. Vi, = 0.1 V , L,; = I . 2 pni

6 - W

9 5 -

4 -

3 -

2 -

n l 1 u,O 0,s 1,0 1,s 2,O 2,s 3,O

VG(V) Fig. 8. Simulation of f ,>(V(,) curve shift versus trapped charges position. No* = 1.2 X 10'' cm I , AX = 0.15 pm. X, , , , , , referred to the middle of the transistor (poly edge: 0 .65 p m ) .

3

2 :il 1

J

" u,O 0,s 1,0 1,s 2,O 2,s 3,O

V G ( W Fig. 9. Simulation of V<,) curve shilt versus trapped charges density ( cm '). X, , , , , = 0 .6 pm. AX = 0.15 pm. X ,,,,,, referred to the middle of the transistor (poly edge: 0 .65 pm).

VIRGIN Nox=3 loi2 Nox=6 loi2 Nox=l 10'3 P

significant current shift without any noticeable shift in the threshold voltage.

In order to investigate trapping during the aging of the device, we performed PISCES simulations with different amounts of negative trapped charge. The purpose of this work is not to discriminate between negative charges and interface states, both leading to similar effects. Negative charges were chosen for practical simulation reasons. The simulated transistor has a gate length of 1 .3 pm. The neg- ative charges are trapped along a length AX from X,,,, to X,,,,. The X-axis coordinates are referenced from the mid- dle of the transistor (the gate edges at the source side and at the drain side are, respectively, at X = -0.65 pm and X = 0.65 pm).

Fig. 8 shows ZD(VG) shift for different trapping loca- tions, with charges located on a length AX = 0.15 pm with a density NO, = 1.2 x IO" cm-'. We can see that the shift of the curve increases when the trapping charge moves toward the channel of the transistor. When all the charge is located under the gate, a drastic increase of the threshold voltage is observed.

In Fig. 9 we study the influence of the trapping level for a trapped charge located on a length of 0.15 pm, 50 nm under the gate, and 100 nm under the spacer. When the charge density increases, the current first decreases

" u,O 0,s 1,0 1,s 2,O 2,s 3,O

VG(V) Fig. 10. Simulation of I / l ( V c ; ) curve shift versus trapped charges density ( c m - 2 ) . X,,,,,, = 0.65 pm, AX = 0.15 pm. X ,,,,,, referred to the middle of the transistor (poly edge: 0 .65 pm).

without any significant threshold-voltage shift. However, for higher trapped levels, a drastic threshold-voltage shift is observed. Whatever the trapped charge density is, it is not possible to observe a shift of linear current of 10% without any significant shift of the threshold voltage.

Fig. 10 studies the case with all the trapped charge un- der the spacer. No measurable VI shift is observed while the current can drastically decrease by about 30%. In this case, only the serial resistance of the device is affected, not the threshold voltage. It is clear that our experimental case can be completely explained by the simulation of Fig. 10, with all the trapped charge under the spacer. On the other hand, as explained by the case of Fig. 9, simulations cannot fit the experimental data if we assume the charges partially located under the gate.

We tried to fit our experimental data with simulations. A good fit was obtained by assuming a trapped charge of 4.5 x l o i 2 cm-' under the spacer (Fig. 11).

36X 1EE.I- 1RANSACIIONS O N E L b C I K O N DEVICES. V O L 40. N O 2 . FEBRUARY 1993

10 I :

10.':

0 1 , B , , , I , , , 0.000 v VC 5 0 0 . 0 m V / d i v 5.000 v

Fig. 1 1 . Typical shift o f the I , > ( V ( ; ) curve o f HSOI transistor I,,, = I . 3 p m . Comparison between measurement\ and simulations Simulation after stress: N , , , = 4 .5 X cm ', X ,,,,,, = 0.65 pin, AX = 0.15 pin.

VII. INFLUENCE OF THE N - DOPING LEVEL A . Relation Between Trapping and N

We have seen in the previous section that the degra- dation of the SO1 transistor can be explained by trapped negative charges under the spacer. These charges tend to deplete the N - region and then to increase the serial re- sistance. We can now study the correlation of interaction between the trapped charge density and the N - doping level and the degradation of the transistor. Fig. 12 rep- resents the relation between the measured current, the negative trapped charge under the spacer (on a length of 0.15 pm), and the N - implantation dose. Two kinds of curves can be observed: 1) For low values of N - (typi- cally N - = 5 X 10l2 cm-'), the trapped charge can to- tally deplete the N - region until the current completely vanishes. 2) For higher values of N - (typically N - = 5 x cmP2 and more), it is no longer possible to totally deplete the N - . There is inversion at the interface before complete depletion of the N - . When inversion is reached, a saturation of the shift is observed. Moreover, the higher the N doping level, the less the degradation of the tran- sistor.

In the case of our devices, the N - ( I X IO" cm-') cannot be totally depleted but appears to be sensitive to trapping.

Doping

B. Comparison of SOI and BULK Technology In a similar way as Fig. 12, Fig. 13 illustrates the re-

lation between the shift of the transistors parameters (here the linear current) and the trapped charge under the spacer. The two technologies can be compared. For low trapped charge levels, the shift of the HSOI transistor current ap- pears to be much higher than that of the HCMOS transis- tor. For a given N o x , the difference in the shifts corre- sponds to a factor of four. This corresponds approximately to the difference between the effective N doping levels.

For high trapped charge levels, the shift of the bulk transistor saturates for trapped-charge densities much lower than that of the HSOI transistor and this tends also to limit the degradation. In the case of the HCMOS tran- sistor degradation, the parameter shift saturates under 10%. In practice it does not mean that the degradation is

N-= 1.5 1013

N-= 1 1013

N-= 5 lo'* \ , , , , , , ( , , , , , . 1 1

0 1014 l o l l 1 o I 2 1 0 ' ~

Nox ( /cm2)

Fig. 12 . Linear current dependcnce M i th negative trapped charge density (cni '1. I,, meaured at v ~ , = 3 V . v,, = 0. I V . N , , ~ localized under the spacer. X ,,,,,, = 0 65 pm, AX = 0. 15 pni. Parameter: N ~ (cni '1.

10.34 ' ' " " ' 7 ' ' ' ' -I 10" LO" 1 0 ' ~

Nox ( lcm2)

big. I3 Linear current \ h i l t versus negative trapped charge. Comparison HSOIIHCMOS. I,, measured at V,, = 3 V . V,] = 0.1 V . N , , , localized under the spacer: X, , , , , , = 0.65 pin. A X = 0 . IS pili.

limited. The degradation can exceed 10% because of the modification of the degradation mode, with typically an increasing effect of channel trapping.

C. Anulysis of Aging Kinetics f i)r Different N - Fig. 14 shows the aging kinetics for two HCMOS tran-

sistors with respectively N =

7 x 10" cm-'. The first case is the nominal case of the technology and the second one is presented for its analogy with the HSOI case (low N - value).

For N - = 7 X I O ' ? cm-?, we observe a high initial degradation of linear current, associated with the mecha- nism of depletion of N during aging, and a weak deg- radation of G,,,. The degradation of G,,, appears at the high stress times.

For N = 3 x 10" cm -', the degradation of G,,, be- comes predominant more rapidly than the linear current. In this case, the aging of the channel part is more effective than the aging under the spacer.

Among these two N - doses, the lowest leads to the highest lifetime. The improvement induced by the low substrate current predominates compared to its high ten- dency to be depleted. The highest dose is, however, more suitable for the technology because it guarantees a suffi- cient lifetime and a higher current.

Fig. 15 compares the aging kinetics for the HCMOS transistor with modified N = 7 x I O ' * cm-2 and for the

= 3 x I O t 3 cm-? and N

REIMBOLD A N D AUBkK I O N - H k X V I ? AGING A N A I . Y S I S OF nMOS SO1 T t C H N O L O G ~ ' 369

h

AIlh/Ilin N-=7 1012 8 100 + AGm/Gm N-= 7 1012 - AGdGm N-= 3 1013

k + h~wnin ~ - = 3 1013 a U

10

901' "'."I ""- .'.''.l ....-. "".-' l o o 10' i o 2 i o 3 i o 4 i o 5 i o 6 10' 10"

Stress time (s) Fig. 14. Comparison o i aging characteristics tor two N conditions. HCMOS technology. &, = 1.3 pin. Stress: V( , = 3 V. V,, = 8.8 V. I ,,,, measured at V( , = 5 V. = 0. I V.

-AIlinDin HSOI7V +AIldIlin HCMOS 7 1012 8 . 8 ~ -AGm/Gm HCMOS 7 1012 8.8V

g 100

10 U

14 B

Stress time (s) Fig. 15. Comparison of aging characteristics lor different conditions. L(, = 1.3 pm. HCMOS: I,,, measured at VI; = 5 V. V,, = 0.1 V. V,,,,,,,, =

8.8 V. HSOI: I , , , , measured at Vc, = 5 V. V,] = 0 . 5 V. V,,,,,,,, = 7 V.

HSOI transistor with N - = 1 X 10" cm-'. In spite of its higher N - doping value, the HSOI transistor presents at 7 V a lifetime lower than the BULK transistor at 8.8 V. This shows that the low N - doping used in the HSOI technology explains only partly the high degradation. Most of it is explained by the high ionization rate.

VIII. CONCLUSION A N D PERSPECTIVES BULK HCMOS transistors present a high lifetime be-

cause a low ionization rate can be obtained in combination with high N value. A low lifetime is measured for HSOI transistors because a low ionization rate cannot be ob- tained even with low N - . This high ionization rate is a consequence of the steep doping profiles induced by the low-temperature process which limits the diffusion of the N - and by the high channel doping which compensates the N - doping.

If we did not choose to keep a low-temperature process, we could strongly reduce hot carrier effects. Fig. 16 pre- sents the simulation of the electric field for a SO1 transis- tor in which a high-temperature process step (1000°C) has

i ::I , , , , , , , , ,!d W O - ~ _ ~ _ - T-:-- C.0C 0.21 '2.50 C.75 1.00

Distance (Microns)

Fig. 16. Comparison 0 1 electric field for HSOI, HCMOS, and high-tem- perature (1000°C) SO1 transistors. Simulation: L ( , = 1.3 pin. VI; = 2.5 V. V,, = 5 V . Localization = 300 A from interlace.

been introduced at the end of the process (similar to the bulk process). We obtain in this case a smoother profile which leads to an electric field as low as that of the BULK transistor. The lifetime would be highly improved but should remain lower than the lifetime of the BULK tran- sistor because of the lower N -. This confirms that good lifetime characteristics can be obtained, depending on the process margin we can have. This also shows that we must be very careful in comparing different technologies.

For submicrometer technologies, the maximum tem- perature of the process has to be reduced even in the case of BULK technologies. It is necessary to keep low junc- tion depths and to minimize short-channel effects. Ac- cording to the arguments presented in the previous para- graphs, this could reduce the difference between hot carrier susceptibilities.

R E F P,R ENC ES

I . P. Colinge. "Hot-electron effects in silicon~on-insulator n-channel Trm.\. Elec.rr.017 Drr.ic.c., vol. ED-34, no. 10. pp.

2173-2177. 1987. T. Makino and S . Kawamura. "A study of hot-carrier-etfects in SOL- MOSFETs using photon emission." in Errrnded Ahsrrcirrc 1991 / ? 7 l . Crmj. 0 1 7 Solid Srtrrc De~ic,c,.s c r ~ d Mutcritrls (Yokohama, Japan), 1991.

R . Sundarewn and C . E . D. Chen. "Simox devices and circuits." i n P m . . 4rh /f ir . S\VI / I . 011 SOI T ~ , c h ! i o l o ~ \ ~ 1 7 d Drt,ic,e.r. 1990. pp. 437- 454. M . Yoshinii. M. Takahashi. T . Wada. K. Kato, S . Kambayashi. M. Kemmochi. and K. Natori. "Analysis of the drain breakdown mech- anism in ultra-thin-tilm SO1 MOSFET's." IEEE Trcrrls. Elrc.tron DP- ~ , I c , e . \ . vol. 37. no. 9. pp. 2015-2021. 1990. J C;. Fossum. J . Y. Choi. and R . Sundaresan. "SO1 design for com- petitive CMOS VLSI." /E€€ Trtr!is. Elrcrr-on De),icrs. vol. 37. n o . 3. pp. 724-729. 1990. P. H . Woerlee. C. Jutfcrrnans. H LitLa. W. Mandcrs. F. M. Oude Lansink. G . M. Paulren. P. Sheridan. and A. Walker, "A half- micron CMOS technology using ultra-thin silicon on insulator," i n IEDM Tech. Di,g.. 1990. pp. 583-586 G . Reirnhold. P. Saint Bonnet. B. Gitfard and A . J . Auberlon-Hervi. "Influence ot LDD on aging o l SO1 NMOS transistors." in Ah.srrcic~rs o/ I Y Y O SOSISOI Tcchrlologv C O I I , ~ . , SO/ Con71.. pp. 38-39. A . J . Auberton-HerLe. M. Bruel. C . Jaussaud. J . Margail. W . D'Hcs- pel. J . F. Pcrc. A Viter. and A . Tiswt. "A CMOS-SO1 1.4 pm technology o n 1300°C annealed SIMOX substrates without epitaxy ." in /'roc,. I988 S J ~ I . 011 VLSI Tdirlo/og\ . pp. 65-66. G . Reinibold. private communication. LETI-CEA. 199 I . T . Ouisse. Ph.D. dissertation, lNPG Grenoble. France. 1991. M . Simons. G . Cainpisi. and H . L Hughes. "Evaluation of pulsed radiation elt'ects in buried oxides by fast C-V measurements." J . A p p l . P / r ~ . c . . v o l . 70. no. 9. pp. 4784-4789. 1991. F . T. Bradq. J . T . Chu, S. S . Li. and W. Krull. "Low-field charge

pp 20-22.

370 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 40, NO 2. FEBRUARY 1993

injection i n Simox huried oxides.” i n Ah\rrucr 1990 SOS/SOI 7 e t h - Andre-Jacques Auberton-Herve received the r lo /og \ Conf , so/ Conf , pp 158- 159 engineer’\ degree from the Ecole Centrale de

[ 131 T Ouis\e, S Cristolovednu, dnd G Borel. “Hot-carrier-induced Lyon, Lyon, France. in 1983 dnd in the \ame yedr, degraddtion of the back interface in short-chdnnel silicon-on-inwlator the M Sc degree in semiconductor physic\ from MOSFET’s,” / E E E Elecrrori Drrrte Lrrr , vo l 12, no 6, pp 290- St Etienne Univer\ity In 1986. he received the 292. 1991 Ph D degree Hi\ di\\ertation was on micronic

[ 141 Y Yamdguchi. T IWdmdtsU, H Odd. Y Inoue, T Nishimura, dnd SOI-MOS procc\\e\ and modeling in th in SO1 Y Akdsaka, “Structure design tor submicron MOSFET on ultrd t h i n SOI.” in IEDM r r t h Dig , 1990, pp 591-594 In 1986 he joined LETl Laboratory ( a d iv i \ ion

front chdnnel chdrdcteristic\ in thin-film SO1 MOSFET’\,” f E E E

films

[ I S ] B Zhang and T P Ma. “Back-channel hot-electron effect o n the of the French Coinmissdridt a I‘Energie Ato niique). Grenoble. to develop d 1 2-pm CMOS

Lrrr , vol 12, no 12, pp 699-701. 1991 SO1 technology by using SlMOX sub\trdtes Since 1987 he has been VLSI- [ 161 P H Woerlee. A H van Ommen, H L i h . C A H JUffermdn\. SO1 Technology Manager at LET1 He I\ in charge of the micrometer and

L Pldjd, and F M Klaa\sen, ”Half-micron CMOS on ultrd-thin \ i I wbmicrometer CMOS-SO1 technology development in a joined progrdm of icon on inwldtor,” in l t D M Tech Dig , 1989. pp 821-824 Thomson-CSF dnd LETl

1171 C Hu . S C Tam, F C Hsu, P K KO, T Y Cham, and K W Terrill, “Hot-electron-induced degradation-Model, monitor dnd i n - provement,” /EEE Trtrns Elrcrrori Drir t rc . v o l ED-32. no 2 . pp 375-385. 1985

Gilles Reimbold was born in Chateauroux. France. He received the engineer degree in elec- tronics from the National Polytechnic Institute of Grenoble, Grenoble, France. in 1980 and the En- gineer Doctor degree in 1983. on the topic of noise in MOS transistors and CCD.

He joined the LabordtOirC d’Electronique et de Technologie de I’lnformatique (LETI). Grenoble, in 1983 to work in VLSI technology development. Currently he is managing reliability activities.

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