2013030131

2009030098

1

1

1) LED0=BTN0*(IN0*IN1)

2) LED1=BTN1*(IN0 XOR IN1)

3) LED2=BTN2*(IN0 NOR IN1)

4) LED3=BTN3*IN0

5) LED4=IN0

6) LED5=IN1

2

Half Adder

library ieee;

use ieee.std_logic_1164.all;

entity half_adder is port (x, y : in std_logic; s, c : out std_logic);

end half_adder;

architecture dataflow_3 of half_adder is

begin

s

Full Adder

library ieee;

use ieee.std_logic_1164.all;

entity full_adder is port (x, y, z : in std_logic; s, c : out std_logic);

end full_adder;

architecture struc_dataflow_3 of full_adder is component half_adder port (x, y : in std_logic; s, c : out

std_logic);

end component;

signal hs, hc, LED0: std_logic;

begin

HA1: half_adder

port map ( x => IN0,

y => IN1,

s => hs,

c => hc);

HA2: half_adder

port map ( x => hs,

y => IN2,

s => LED1,

c => LED0);

c