Ηλεκτρονικό πακετάρισμα

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ΜΑΘΗΜΑ: Τεχνικές Συσκευασίας  Ηλεκτρονικών  Συστημάτων ΕΡΓΑΣΤΗΡΙΑΚΕΣ ΑΣΚΗΣΕΙΣ Η σειρά αυτή των εργαστηριακών ασκήσεων σχεδιάστηκε για  να αντιληφθεί ο σπουδαστής μερικά από τα κύρια προβλήματα που αντιμετωπίζει ο μαχόμενος Ηλεκτρονικός Μηχανικός στη σχεδίαση και  υλοποίηση σύγχρονων ηλεκτρονικών συστημάτων και  να διερευνήσει τρόπους επίλυσής των, δεδομένου ότι με την χρήση των μοντέρνων κυκλωμάτων VLSI ένα σημαντικό ποσοστό της μείωσης της ταχύτητας μετάδοσης των σημάτων οφείλεται πλέον στις γραμμές διασύνδεσης μεταξύ των ολοκληρωμένων κυκλωμάτων (off-chip interconnections) και συνολικά στον τρόπο πακεταρίσματος του όλου ηλεκτρονικού συστήματος το οποίο αποτελείται από έναν αριθμό ταχύτατων ολοκληρωμένων κυκλωμάτων. Ειδικώτερα, μιά τέλεια σχεδίαση σύγχρονου ηλεκτρονικού πακεταρίσματος θα πρέπει  να εξετάζει RC interconnection delay, ανακλάσεις σε ασυνέχειες, cross talk, τερματισμό και οδήγηση των γραμμών ρολογιού, θόρυβο γραμμών τροφοδοσίας, κλπ. ΒΙΒΛΙΟΓΡAΦΙΑ 2.  Bakoglu H. B., “Circuits, Interconnections, and Packaging for VLSI”, Addison- Wesley, 1990. 2. Young-Soo Shn,et al. “Empirical Equations on Electrical Parameters of Coupled  Microstrip Lines for Crosstalk Estimation in Printed Circuit Board”, IEEE Transanctions on Advanced Packaging, Vol.24(4)2001. 2.  Brian Young, “Digital Signal Integrity:Modeling and simulation with  Interconnects and Packages”, Prentice Hall Modern Semiconductor Design Series, 2001. Ι.  Ν. Αβαριτσιώτης 2008 1

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Τεχνικές συσκευασίας ηλεκτρονικών συστημάτων, θεωρία, εργαστηριακές ασκήσεις

Transcript of Ηλεκτρονικό πακετάρισμα

  • :

    , VLSI (off-chip interconnections) . , RC interconnection delay, , cross talk, , , . A 2. Bakoglu H. B., Circuits, Interconnections, and Packaging for VLSI, Addison-

    Wesley, 1990. 2. Young-Soo Shn,et al. Empirical Equations on Electrical Parameters of Coupled

    Microstrip Lines for Crosstalk Estimation in Printed Circuit Board, IEEE Transanctions on Advanced Packaging, Vol.24(4)2001.

    2. Brian Young, Digital Signal Integrity:Modeling and simulation with Interconnects and Packages, Prentice Hall Modern Semiconductor Design Series, 2001.

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  • :

    (off-chip interconnections)

    (drivers)

    ,

    .

    1. .:

    1: chip

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  • :

    :

    ( ) :

    noise margin . .

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  • 2. PCBs (Printed Circuit Board) , lossless transmission lines. , , lumped capacitive inductive loads. : . , (LdI/dt).

    2 & :

    3

    , SPICE PCB ,

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  • () lumped elements. - D ( MCM-D). :

    4

    , - fringing fields. , , , , . PCB, TEM-mode (Transverse Electro-Magnetic) , Maxwell , ,

    ( 1).

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  • : Bakoglu H. B., Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990. time-of-flight (ToF)

    l L, C . ,

    :

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  • lumped capacitance mode. PCB (impedance) :

    =r0 5

    :

    (ground plane) . ,

    PCBs , ,

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  • vias, .

    5% W/h

  • 4. & wire bonds, vias , .

    CMOS (. ) . :

    , , , (1+). .

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  • , motherboard, , .

    6

    . :

    :

    :

    :

    :

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  • :

    :

    ri

    VV

    =

    :

    :

    5.

    ToF . ,

    tr < 2.5 tf , , lumped elements

    tr > 5 tf

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  • . 10 cm, , 1.5 nsec. : ) . . ) . . . 6. Cm ,Cs

    :

    :

    1mil=0.00245cm

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  • : !!!!!

    I:

    : &

    : PCB ORCAD ( PSPICE). . pads 150mm. 170mm X 170mm.

    7

    A) W=1mm S=0.3mm S=0.4mm S=0.5mm S=0.6mm ) W=2mm S=0.4mm S=0.6mm ) W=3mm S=0.3mm S=0.6mm S=0.9mm S=0.9mm ground plane

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  • : photoresist :

    8: ground plane .

    ground plane. H .

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    pads

    10 : pads 2mmX4mm .

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  • .

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    . ( ) laser printer inkjet printer ( 600dpi) . . PCB .

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  • I: : &

    : . . 1. (ground plane) PCB ( ). : . LCR meter HP : ) (mutual inductance) (self-inductance) .

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    paper. (Young-Soo Shn,et al. Empirical Equations on Electrical Parameters of Coupled Microstrip Lines for Crosstalk Estimation in Printed Circuit Board, IEEE Transanctions on Advanced Packaging, Vol.24(4)2001). B) , , Rp RS Zo . . 2. () LCR meter : ) (self capacitance) ) (mutual capacitance)

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  • 1.

    epoxy glass. 2.

    . . 3. . 4.

    5. 5. 1-section lumped circuit model ( 3) PSPICE,

    Zo 6.

    PSPICE. .

    REPORT .

    Z L self L mutual C self C mutual Zo Ls Rs Ls Rs Cp Rp Cp Rp W = 1

    S = 0.3

    S = 0.4

    S = 0.5

    S = 0.6 W = 2

    S = 0.4

    S = 0.6

    W = 3

    S = 0.3

    S = 0.6

    S = 0.9 S = 0.9 no ground

    r T H

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  • I:

    : CROSSTALK

    : crosstalk . PSPICE. crosstalk:

    S/W

    Cm/Ct . Lm/Ls .

    .

    1. ( ) 5Volt. 0Volt 5Volt. rise time 10 nsec 100Hz. . , , : ) (near end) ( ). : . ) probe (far end) .. ) rise time 10 msec 100Hz. 2. 13 .

    13

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  • 3. 14 .

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    4. ( ) 5Volt. 0Volt 5Volt. rise time 10 nsec 100Hz. . ( ) :

    , , : ) (near end) Z0 100100 0 R2 R1. : . ) R1 crosstalk . Young-Soo Shn,et al. Empirical Equations on Electrical Parameters of Coupled Microstrip Lines for Crosstalk Estimation in Printed Circuit Board, IEEE Transanctions on Advanced Packaging, Vol.24(4)2001 crosstalk :

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  • : Vswing = 5Volt,

    150 mm .

    1. crosstalk near end far end epoxy glass .

    2. . 3. crosstalk

    S/W . 4. . 5. R1 ,

    crosstalk, . .

    6. 1-section lumped circuit model PSPICE, 3 crosstalk.

    7. crosstalk. REPORT .

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  • I:

    :

    : ToF . :

    15

    lumped RC :

    :

    tRC

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  • , :

    10% 90% :

    ToF

    :

    :

    :

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  • (ringing) (overshoots). , buffer settling time . , . far end . 1. ( ) W=1mm

    & S=0.2mm, 5Volt p-p 1MHz, 2 0 Ohm. 50. (ground plane) PCB .

    2.

    (near end) ( ) ( ).

    3. . HP-IB interface.

    4. . .

    5. .

    6. . .

    7. 1,2,3 & 4 far end . ( 100)

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  • .

    . REPORT .

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  • II:

    &

    : . dI/dt buffers . Faraday , emf = -(d/dt). =LI emf=-L(dI/dt), L . :

    16: IC ( mutual

    inductance signal power/ground planes) , ECL (Emitter Coupled Logic)

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  • 17: ECL

    R1 R2 ( ECL ) . group R2 Vx switches over R1 R2 . 2 off I1 =(VDD/R1). A 2 , Lext chip V VDD. :

    :

    , group 2 turns on ,

    R1 < 0.1 R2 10% .

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  • II: : (tr) ( nsec). . 1. :

    18

    2. 10V dc .

    3. 22222.

    4. R4 .

    5. R4 20kHz. 6. ( )

    22222 ( 50 60 nsec). , .

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  • II: :

    1.

    R1

    19

    2. 1 22222

    . 3. ( AC coupling) 2

    . .

    4. A 180nF R1.

    5. ( AC coupling) 2 . k

    6. A R1 100 R1 1.2 R2 ( 100).

    7. ( AC coupling) 2 ( 22222) . .

    .

    REPORT .

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  • ORCAD LAYOUT Plus Lite

    1. Orcad Layout-Lite edition File>New

    . METRIC.TCH

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  • Cancel.

    Layout Plus-Lite Edition

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  • layers (. TOP, BOT, GND ..)

    obstacle tool , .

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  • mouse button Properties

    obstacle edit. layer , . .. Free Track layer TOP , Copper area PADS TOP Layer Ground Plane Bottom Layer.

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  • mouse End Command. .

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  • grid. grid spacing : Options->System Settings

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  • grid spacing layout. 2. (MANUAL DESIGN) , 0.3mm 0.6mm. ( ). . artwork. , 200mm150mm. global layer obstacle type Board outline.

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  • grid spacing .

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  • board outline , .. ( DISTANCE).

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  • To grid spacing . . grid zoom in. .

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  • obstacle type Free track ( 1mm) Layer.

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  • . PageUp/PageDown.

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  • (. 0.3mm) .

    (0.3mm) (1/2mm=0.5mm).

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  • PADS .

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  • PADS layer Copper area Obstacle Tool, Width :

    (Ground Plane) PADS Copper Area Bottom Layer. 3. Text Tool layer . New Text String Layer ( TOP)

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  • 4. :

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  • 5. ARTWORK layout Options>Post Process Settings

    Post process. layers .

    layers layout . . layer TOP mouse Batch Enabled

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    Output Format Print Manager. Force Black & White. layer

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  • Options Enable for Post processing.

    layout laser inkjet printer Transparent Films laser inkjet printer.

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  • :

    1. PADS 2mm4mm 2. PADS 1mm

    6.

    (.. ) ( Obstacle Tool, , Obstacle Tool)

    Edit -> Copy. .

    Home F5 Redraw , Orcad .

    Page Up / Page Down I / Z zoom in / zoom out

    . Text Tool

    layer . New Text String Layer ( TOP)

    7.

    . UV .

    .

    UV.

    1) (steel) . . .

    2) 3) 15

    4) 10

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  • 5) UV 230. 6)

    developer () .

    To 0.20mm : positive photoresist .

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  • Orcad 9.2 Lite Edition

    Capture CIS project. File>New>Project project PCB Board Wizard

    project. . .

    , project. Analog, Discrete Transistor. .

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  • , .

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  • footprints , layout . footprints . Layout Plus Lite Edition, . Tools Library Manager.

    footprints. PACKAGING_2004, . , .rar . , Library Manager Add . Footprints footprints .

    footprints . , PCB Footprint, Library Manager. , PCB Footprint 22646 22646 ( ).

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  • , . Layout Plus .

    Layout , Tools Create Netlist. , Layout *.MNL, project.

    User properties are in millimeters. Layout Plus.

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  • Layout, File > New. technology template . technology templates .TCH standards , , Gerber. .TCH Orcad Layout_Plus\Data . METRICH.TCH.

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  • , .L , .

    .MAX , project Layout . , layout footprints .

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  • Layout Move Datum (Tool>Dimension>Move Datum). , .

    Obstacle Tool Board Outline ( Global Layer, .. 0,5 mm) 5cmx5cm. Outline . Board Outline . .

    Track (Tool>Track>Select tool) , . (2mm).

    , pads ( Obstacle, Copper area) , ( Text tool) . :

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  • :

    1) Bottom Layer , pads.

    2) . ( pad) .

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    Orcad 9.2 Lite Edition footprints Layout Layout