Toru Tsuboyama (KEK)4 July 2008

Leader: Y. Arai (KEK)Activity started as one of KEK detector R&D projects in 2005. Three multi-project wafers have been submitted (2005, 2006 and 2007) to OKI 0.15/0.20 μm SOI CMOS.

Multiple-Project Wafer: KEK, Jaxa, Hawaii, FNAL and LBL.Submission 2005/2006/2007

Contents1. Introduction2. SOI structure3. Radiation hardness4. Test of pixel sensor prototypes

The charge induced by radiation in the silicon wafer is processed by CMOS circuit above the buried oxide (BOX).

Process 0.15μm Fully-Depleted SOI CMOS process, 1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.).

SOI wafer Wafer Diameter: 150 mmφ, Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thick Buried Oxide: 200 nm thickHandle wafer: Cz、700 Ω-cm (n-type), 650 μm thick (SOITEC)

Backside Thinned to 350 μm, and plated with Al (200 nm).

Improvement is done by modifying design and process parameters

The guard ring structureAvoid square corners

Implantation voltage.The higher the implantation voltage, the deeper the implant depth.Then the maximum electric field is decreased.

4

FY05 FY06ST

FY06HE

Irradiation to proton beam and 60Co γray.Up to 4.7M Gy (470 Mrad)!

5

6

5.8x1014

5.5x1015

・VOUT・RESET

100us/div

6.4x1013

6

Irradiation to Proton beam

– Response of INTPIXEL sensor to reset pulse is measured as a function of proton flux (70 MeV).

– Flux 6.4x1013 , 5.8x1014 ,5.5x1015 neq/cm2

– Response were confirmed up to 5.8x1014 neq/cm2

7

Irradiation to γ

Non-irrad 596 kGy

Vrst [V] Vrst [V]

ActiveBelow threshold

SaturatedWith back-side voltage correction, the pixel circuit functions after 60 Mrad irradiation.

Back Bias

8

Positive charge is accumulated in oxide layer after irradiation.

The accumulated charge changes the characteristics of the transistors.

Can be restored by adjusting the voltage of the substrate silicon.

Back-gate voltage Correction

source draingate

BuriedOxide

Si- substrate

Backgate

+++++

+++

未照射

0 -10 -20 -30

（陽子線照射時）

Vgs[V]

I d [A

]

9 9

INTPIX2005---- 32x32 (0.15 μm)2006---- 128x128 (0.15 μm)2007---- 128x128 (0.20 μm)

10

INTPIX2 Pixel

10

20x20 um2

p-n junction

2008.4.24 Y.Arai(KEK) @DTP Review 11 11

128x128 cells5x5 mm2 chip

2008.4.24 Y.Arai(KEK) @DTP Review 12

Compound Operational Board InterfaceDeveloped by Hawaii groupFADC-FPGA-USB interface

COBI

12

USB

FPGA

INTPIX

Periodical readout and reset is necessaryEvaluation of the pixel structure.Response to pulsed laser and MIP particles was confirmed.

Cluster energy distributionWith 90Sr β source

A prototype pixel sensor for the Belle SVD upgrade was submitted in Dec 2007.

Continuous sampling + comparator + digital pipeline.Implemented in 60x60 μm2 cell.More room to shrink the pixel size.

Trigger Latency

p-n junctions

Analog

Flip-flops

Register Comparator

Prototype 48x48 calls5x5 mm2 chip

4 8 x 4 8 pixels

60umx

60um

DOUT[1 5 :0]

RowAddressDecoder

BiasVrefs

RA[5:0]ENRD

Reset

Vths

XTrigAll

ClearTrigger

YTrig[1 1:0]

YTrigAll

XTrig[1 1:0]

CA[5:0]Column Address Decoder

CIO[4 :0]

Write

OR4

OR4

Submission 2005/2006 2007Technology profile 0.15 μm 0.2 μmWafer Diameter 6 inches 8 inches

Core (I/O) Voltage 1.0V (1.8V) 1.8V (1.8/3.3V)

Gate Length 0.14 μm 0.2 μm

Gate Oxide Thickness 2.5/5 nm 4.5/7 nm

BOX Thickness 200 nm 200 nm

Ioff <100 pA/μm <0.1 pA/μm