. Compulsory, Conflict Capacity misses,

; associativity, block cache.

sets. compulsory misses associativity

cache. capacity misses, capacity cache . conflict misses ,

associativity mapped set.

block, associativity sets.

cache. sets ways conflict misses .

capacity misses. , compulsory misses, block spatial locality

prefetching cache miss. sets

block cache. associativity. compulsory misses

cache. capacity misses,

. associativity conflict misses., Tomasulo

WAR WAW hazards; RAW hazards; O Tomasulo

register renaming WAR, WAW hazards. destination register, 2 hazard

. RAW ,

destination , . register renaming

RAW hazards. Reservation Stations Reorder Buffer; RS

. , ROB ( ) commit.

Branch Target Buffer (BTB); ;

/; target address Taken.

, target

branch ( ).

, ( )

/.

. : (.. bypassing missing writes write-buffers) :

tuning ( SC),

(.. barriers/barriers ).

MESI Exclusive state MSI;

. , block E bus transaction ,

cache .

. associativity tags cache . cache lines ,

tags.

. direct-mapped cache conflict misses . cache

lines L 2L. , i i+L cache, conflict.

. direct-mapped cache compulsory misses . cache lines,

cache line . compulsory misses .

. cache line compulsory misses . line size

cache line cache.

, compulsory miss.

Tomasulo . O Tomasulo out-of-order . program order , blocked . instruction stream. branch path . , , branch ooo . Tomasulo Reorder Buffer. loads (. ); stores (. ); . loads ( EX ). stores CMT. H (speculative execution). loads architectural state EX. , stores ( exceptions/interrupts mispredicted branches). snooping directory ; 2 ; snooping controllers caches . , directory , sharers block, caches . broadcasts directory snooping . Test-and-Test-and-Set (lock) Test-and-Set write-invalidate cache coherence protocol; test-and-set , lock , lock. test-and-set loop, lock invalidations cache line lock, . lock , . , test-and-test-and-set , loop lock lock, , . , , spinning caches , . Update Protocols block caches. block caches. transaction. block transactions . Invalidation vs. Update Protocols cache block. block, ; :Invalidation: Read-miss transactionsUpdate: Read-hit transaction :Invalidation: bus,

Update: ( ). A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor occur in this sequence in the order specified by its program.TestAndSet:mov r1,r2|ld r1,0(&lock)|st r2,0(&lock) TestAndTestAndSet: ld r1, 0(&lock)|bnez r1, A0|addi r1,1,r1|t&s r1 0(&lock)|bnez r1,A0