VHDL για Σχεδιασμό Συνδυαστικών Κυκλωμάτων

Πανεπιστήμιο ΚύπρουΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών

VHDL VHDL για Σχεδιασμόγια ΣχεδιασμόΣυνδυαστικών ΚυκλωμάτωνΣυνδυαστικών Κυκλωμάτων

Διδάσκουσα: Μαρία Κ. Μιχαήλ

ΗΜΥΗΜΥ-210: -210: ΣχεδιασμόςΣχεδιασμός Ψηφιακών ΣυστημάτωνΨηφιακών Συστημάτων

ΧειμερινόΧειμερινό Εξάμηνο Εξάμηνο 200 20077

25/04/23 MKM - 2VHDL για Σχεδιασμό Συνδυαστικών Κυκλωμάτων

VHDL (revisited)VHDL (revisited) VHDL is a hardware description language VHDL is a hardware description language

used to specify logic designs.used to specify logic designs. Sponsored (early 80s) by IEEE and DoD.Sponsored (early 80s) by IEEE and DoD. Features:Features:

Hierarchical designsHierarchical designs InterfaceInterface and and behaviorbehavior specified precisely specified precisely

(and separately)(and separately) Algorithmic or hardware-oriented behavior specAlgorithmic or hardware-oriented behavior spec Concurrency, timing, clocking can be modeled; Concurrency, timing, clocking can be modeled;

design can be simulated accurately.design can be simulated accurately.


VHDL Model ComponentsVHDL Model Components A complete VHDL component A complete VHDL component

description requires a VHDL description requires a VHDL entityentity and a VHDL and a VHDL architecture:architecture: The entity defines a component’s The entity defines a component’s

interface (name, inputs, outputs).interface (name, inputs, outputs). The architecture defines a The architecture defines a

component’s function.component’s function. Several alternative architectures Several alternative architectures

may be developed for use with may be developed for use with the same entity.the same entity.


Simple example: EntitySimple example: Entityentityentity My_Component My_Component isis -- “My_Component”: name of -- “My_Component”: name of

itemitemportport ((XX,,YY:: inin BITBIT;; -- interface specification-- interface specification ZZ:: outout BITBIT););

endend My_Component; My_Component;

CommentsVHDL keywordsIdentifiersPort ModeData Type

My_ComponentX

YZ

port statement defines inputs and outputs


Simple example: Simple example: ArchitectureArchitecture

entityentity My_Component My_Component isis -- “My_Component”: name of -- “My_Component”: name of itemitemPortPort ((XX,,YY:: inin BITBIT;; -- interface specification-- interface specification ZZ:: outout BITBIT););

endend My_Component; My_Component;

ArchitectureArchitecture My_Component_Arch My_Component_Arch ofof My_Component My_Component isisbeginbegin

Z Z <=<= ‘1’ ‘1’ whenwhen X X==‘1’ ‘1’ andand Y Y==‘0’ ‘0’ elseelse ‘0’ ‘0’;;endend My_Component_Arch; My_Component_Arch;

CommentsVHDL keywordsIdentifiersPort ModeData Type

Z = X•Y’ Corresponding entity


VHDL Language elementsVHDL Language elements Comments: start with Comments: start with ----, go to end of , go to end of

lineline Keywords (reserved words): Keywords (reserved words): entity, entity,

port, is, in, out, end, architecture, begin, port, is, in, out, end, architecture, begin, end, when, elseend, when, else,, etcetc..

Identifiers (user-defined ‘variables’)Identifiers (user-defined ‘variables’)


IdentifiersIdentifiers May contain A-Z, a-z, 0-9, _May contain A-Z, a-z, 0-9, _ Must start with letterMust start with letter May not end with _May not end with _ May not include two consecutive _May not include two consecutive _ VHDL is case insensitiveVHDL is case insensitive

Sel, sel and SEL refer to same objectSel, sel and SEL refer to same object


Identifier ExamplesIdentifier Examples A2GA2G

validvalid 8bit_counter8bit_counter

invalid -- starts with numberinvalid -- starts with number _NewValue_NewValue

invalid -- starts with _invalid -- starts with _ first#first#

invalid -- illegal characterinvalid -- illegal character


VHDL Data ObjectsVHDL Data Objects ConstantConstant VariableVariable SignalSignal File*File*

* Not supported by synthesis tools


Characters and StringsCharacters and Strings CharactersCharacters

‘‘A’, ‘0’, ‘1’, ‘$’, ’x’, ‘*’A’, ‘0’, ‘1’, ‘$’, ’x’, ‘*’ StringsStrings

““string of characters”string of characters” ““00101101”00101101” ““0X110ZZ1”0X110ZZ1”

Bit StringsBit Strings B”011111010110”B”011111010110” O”3726”O”3726” X”7D6”X”7D6”


VHDL Data TypesVHDL Data Types ScalarScalar

IntegerInteger EnumeratedEnumerated Real (floating point)*Real (floating point)*

CompositeComposite ArrayArray RecordRecord

Access (pointers)*Access (pointers)*

* Not supported by synthesis tools


Scalar Data TypesScalar Data Types Integer: Integer:

Minimum range for any implementation as Minimum range for any implementation as defined by standard: - 2,147,483,647 to defined by standard: - 2,147,483,647 to 2,147,483,6472,147,483,647

Example: assignments to a variable of type Example: assignments to a variable of type integer :integer :ARCHITECTURE test_int OF test ISBEGIN

PROCESS (X)VARIABLE a: INTEGER;

BEGINa := 1; -- OKa := -1; -- OKa := 1.0; -- illegal

END PROCESS;END test_int;


Scalar Data Type (cont.)Scalar Data Type (cont.)

Integer (cont.): Integer (cont.): We can also define range of integers.We can also define range of integers. Examples:Examples:

typetype CountValue CountValue isis rangerange 0 0 toto 15; 15;typetype Twenties Twenties isis rangerange 20 20 toto 29; 29;typetype Thirties Thirties isis rangerange 39 39 downtodownto 30; 30;


TYPE binary IS ( ON, OFF );... some statements ...ARCHITECTURE test_enum OF test ISBEGIN

PROCESS (X)VARIABLE a: binary;

BEGINa := ON; -- OK... more statements ...a := OFF; -- OK... more statements ...

END PROCESS;END test_enum;

Scalar Data Types Scalar Data Types (cont.)(cont.)

Enumerated:Enumerated: User specifies list of possible valuesUser specifies list of possible values

Example declaration and usage of enumerated data Example declaration and usage of enumerated data type :type :


Booleans Booleans type boolean is (false, true);variable A,B,C: boolean;C := not AC := A and BC := A or BC := A nand BC := A nor BC := A xor BC := A xnor B

VHDL Object

Assignment operator for variables


BitsBits

type bit is (‘0’, ‘1’);signal x,y,z: bit;x <= ‘0’;y <= ‘1’;z <= x and y; VHDL Object

Assignment operator for variables


Standard LogicStandard Logictype std_logic is ( ‘U’, -- Uninitialized

‘X’ -- Forcing unknown‘0’ -- Forcing zero‘1’ ); -- Forcing one

std_logic is part of the std_logic is part of the ieeeieee packagepackage Packages:Packages: precompiled VHDL code stored precompiled VHDL code stored

in a directory referred to as in a directory referred to as librarylibrarylibrary IEEE;use IEEE.std_logic_1164.all; Must be included in your

source code before declaring std_logic data types


TYPE data_bus IS ARRAY(0 TO 31) OF BIT;

VARIABLE X : data_bus;VARIABLE Y : BIT;

Y := X(12); -- Y gets value of element at index 12

0 310 1 ... element indices......array values...

Composite Data TypesComposite Data Types Array:Array:

Used to group elements of the same type into a single Used to group elements of the same type into a single VHDL objectVHDL object

Range may be unconstrained in declarationRange may be unconstrained in declaration Range would then be constrained when array is Range would then be constrained when array is

usedused Example declaration for one-dimensional array Example declaration for one-dimensional array

(vector) :(vector) :


VHDL Architecture VHDL Architecture StructureStructure

architecture name_arch of name is

begin

end name_arch;

Signal assignments

Concurrent statements


Process 1

Process 2


Processes contain sequentialstatements, but executeconcurrently within the

architecture body


VHDL ProcessVHDL ProcessP1: process (<sensitivity list)<variable declarations>begin <sequential statements>end process P1;

Optional process label

Within a process:Variables are assigned using :=and are updated immediately.Signals are assigned using <=and are updated at the end ofthe process.


2-to-4 decoder in VHDL: 2-to-4 decoder in VHDL: Gate-level diagramGate-level diagram


2-to-4 decoder in VHDL: 2-to-4 decoder in VHDL: InterfaceInterface

-- 2-to-4 Line Decoder: Structural VHDL Description-- 2-to-4 Line Decoder: Structural VHDL Description-- (See Figure 3-13 for logic diagram)-- (See Figure 3-13 for logic diagram)library library ieee, lcdf_vhdl;ieee, lcdf_vhdl;

use use ieee.std_logic_1164.ieee.std_logic_1164.all, all, lcdf_vhdl.func_prims.lcdf_vhdl.func_prims.all;all;

entity entity decoder_2_to_4decoder_2_to_4 is isport(port(E_n, A0, A1:E_n, A0, A1: in in std_logicstd_logic;;

D0_n, D1_n, D2_n, D3_n:D0_n, D1_n, D2_n, D3_n: out out std_logic std_logic););

end end decoder_2_to_4;decoder_2_to_4;

Import library Import library functionsfunctions

Inputs & Inputs & outputsoutputs


2-to-4 decoder in VHDL: 2-to-4 decoder in VHDL: Structural ArchitectureStructural Architecture

architecturearchitecture structural_1 structural_1 ofof decoder_2_to_4 decoder_2_to_4 isiscomponentcomponent NOT1 NOT1

portport(in1: (in1: inin std_logic; std_logic;out1: out1: outout std_logic); std_logic);

end componentend component;;componentcomponent NAND3 NAND3

portport(in1, in2, in3: (in1, in2, in3: inin std_logic; std_logic; out1: out1: outout std_logic); std_logic);end component; end component;

Declare Declare available available

componentscomponents


signalsignal E, A0_n, A1_n: std_logic; E, A0_n, A1_n: std_logic;beginbegin

g0: NOT1 g0: NOT1 port mapport map (in1 => A0, out1 => A0_n); (in1 => A0, out1 => A0_n);g1: NOT1 g1: NOT1 port mapport map (in1 => A1, out1 => A1_n); (in1 => A1, out1 => A1_n);g2: NOT1 g2: NOT1 port mapport map (in1 => E_n, out1 => E); (in1 => E_n, out1 => E);g2: NAND3 g2: NAND3 port mapport map (in1 => A0_n, in2 => A1_n, (in1 => A0_n, in2 => A1_n,

in3 => E, out1 => D0); in3 => E, out1 => D0);g3: NAND3 g3: NAND3 port mapport map (in1 => A0, in2 => A1_n, (in1 => A0, in2 => A1_n,

in3 => E, out1 => D1); in3 => E, out1 => D1);g4: NAND3 g4: NAND3 port mapport map (in1 => A0_n, in2 => A1, (in1 => A0_n, in2 => A1,

in3 => E, out1 => D2); in3 => E, out1 => D2);g5: NAND3 g5: NAND3 port mapport map (in1 => A0, in2 => A1, (in1 => A0, in2 => A1,

in3 => E, out1 => D3); in3 => E, out1 => D3);endend structural_1; structural_1;

Local Local signalssignals

2-to-4 decoder in VHDL: 2-to-4 decoder in VHDL: Structural Architecture (cont.)Structural Architecture (cont.)


-- 2-to-4 Line Decoder: Dataflow VHDL Description-- 2-to-4 Line Decoder: Dataflow VHDL Description -- (See Figure 3-14 for logic equations)-- (See Figure 3-14 for logic equations)

librarylibrary ieee, lcdf_vhdl; ieee, lcdf_vhdl;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall, lcdf_vhdl.func_prims., lcdf_vhdl.func_prims.allall;;entityentity decoder_2_to_4 decoder_2_to_4 isis

portport(E_n, A0, A1: (E_n, A0, A1: inin std_logic; std_logic; D0_n, D1_n, D2_n, D3_n: D0_n, D1_n, D2_n, D3_n: outout std_logic); std_logic);endend decoder_2_to_4; decoder_2_to_4;

2-to-4 decoder in VHDL: 2-to-4 decoder in VHDL: Dataflow ArchitectureDataflow Architecture


architecturearchitecture dataflow_1 dataflow_1 ofof decoder_2_to_4 decoder_2_to_4 isissignalsignal A0_n, A1_n: std_logic; A0_n, A1_n: std_logic;beginbegin

A0_n <= A0_n <= notnot A0; A0;A1_n <= A1_n <= notnot A1; A1;E_n <= E_n <= notnot E; E;D0_n <= D0_n <= notnot (A0_n (A0_n andand A1_n A1_n andand E); E);D1_n <= D1_n <= notnot (A0 (A0 andand A1_n A1_n andand E); E);D2_n <= D2_n <= notnot (A0_n (A0_n andand A1 A1 andand E); E);D3_n <= D3_n <= notnot (A0 (A0 andand A1 A1 andand E); E);

endend dataflow_1; dataflow_1;

2-to-4 decoder in VHDL: 2-to-4 decoder in VHDL: Dataflow Architecture Dataflow Architecture

(cont.)(cont.)


Another example:Another example:An n-line 4 x 1 multiplexerAn n-line 4 x 1 multiplexer

a(n-1:0)b(n-1 :0)

y(n-1 :0)

sel(1:0)

8-line4 x 1MUXc(n-1 :0)

d(n-1 :0)

Sel y“00” a“01” b“10” c“11” d


library IEEE;use IEEE.std_logic_1164.all; entity mux4g is

generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) );end mux4g;

An n-line 4 x 1 multiplexer:An n-line 4 x 1 multiplexer:Entity DeclarationEntity Declaration


architecture mux4g_arch of mux4g isbegin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process;end mux4g_arch; Must include ALL posibilities

in case statement

Sel y“00” a“01” b“10” c“11” d

An n-line 4 x 1 multiplexer:An n-line 4 x 1 multiplexer:Dataflow architecture Dataflow architecture

declaration using a CASE declaration using a CASE statementstatement


Half AdderHalf Adder Problem: Model a single bit half adder with carry Problem: Model a single bit half adder with carry

and enable.and enable. SpecificationsSpecifications

Inputs and outputs are each one bitInputs and outputs are each one bit When enable is high, result gets x plus yWhen enable is high, result gets x plus y When enable is high, carry gets any carry of x plus yWhen enable is high, carry gets any carry of x plus y Outputs are zero when enable input is lowOutputs are zero when enable input is low

xy

enable

carryresultHalf Adder


Half Adder: Entity Half Adder: Entity DeclarationDeclaration

As a first step, the entity declaration As a first step, the entity declaration describes the interface of the describes the interface of the componentcomponent input and output input and output portsports are declared are declared

xy

enable

carryresult

HalfAdder

ENTITY half_adder IS

PORT( x, y, enable: IN bit; carry, result: OUT bit);

END half_adder;


Half Adder: Behavioral Half Adder: Behavioral Architectural Architectural SpecificationSpecification

A high level description can be used to A high level description can be used to describe the function of the adderdescribe the function of the adder

The model can then be simulated to verify correct functionality of the component

ARCHITECTURE half_adder_a of half_adder ISBEGIN

PROCESS (x, y, enable)BEGIN

IF enable = ‘1’ THENresult <= x XOR y;carry <= x AND y;

ELSEEND IF;

END PROCESS;END half_adder_a;


As a second method, a structural description can As a second method, a structural description can be created from pre-described componentsbe created from pre-described components

These gates can be pulled from a library of parts, and the functionality, again, can be simulated

xy

enablecarry

result

Half Adder: Structural Half Adder: Structural Architectural Architectural Specification Specification


ARCHITECTURE half_adder_c of half_adder_Nty IS

COMPONENT and2PORT (in0, in1 : IN BIT;

out0 : OUT BIT);END COMPONENT;

COMPONENT and3PORT (in0, in1, in2 : IN BIT;


COMPONENT xor2PORT (in0, in1 : IN BIT;


FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);

-- description is continued on next slide

Half Adder: Structural Half Adder: Structural Architectural Specification Architectural Specification

(cont.)(cont.)


-- continuing half_adder_c description

SIGNAL xor_res : bit; -- internal signal-- Note that other signals are already declared in entity

BEGIN

A0 : and2 PORT MAP (enable, xor_res, result);A1 : and3 PORT MAP (x, y, enable, carry);X0 : xor2 PORT MAP (x, y, xor_res);

END half_adder_c;

Half Adder: Structural Half Adder: Structural Architectural Specification Architectural Specification

(cont.)(cont.)


A 3rd method is to use logic equations A 3rd method is to use logic equations to develop a data flow descriptionto develop a data flow description

Again, the model can be simulated at this level to confirm the logic equations

ARCHITECTURE half_adder_b of half_adder_Nty ISBEGIN

carry <= enable AND (x AND y);

result <= enable AND (x XOR y);END half_adder_b;

Half Adder: Dataflow Half Adder: Dataflow Architectural SpecificationArchitectural Specification


4-bit adder:4-bit adder:Entity declarationEntity declaration

-- 4-bit Adder: Behavioral Description-- 4-bit Adder: Behavioral Descriptionlibrarylibrary ieee; ieee;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall;;useuse ieee.std_logic_unsigned. ieee.std_logic_unsigned.allall;;

entityentity adder_4_b adder_4_b isisportport(B, A : (B, A : inin std_logic_vector(3 std_logic_vector(3 downtodownto 0); 0);

C0 : C0 : inin std_logic; std_logic;S : S : outout std_logic_vector(3 std_logic_vector(3 downtodownto 0); 0);C4: C4: outout std_logic); std_logic);

endend adder_4_b; adder_4_b;


architecturearchitecture behavioral behavioral ofof adder_4_b adder_4_b isis

signalsignal sum : std_logic_vector(4 sum : std_logic_vector(4 downtodownto 0); 0);

beginbeginsum <= ('0' & A) + ('0' & B) + ("0000" & C0);sum <= ('0' & A) + ('0' & B) + ("0000" & C0);C4 <= sum(4);C4 <= sum(4);S <= sum(3 S <= sum(3 downtodownto 0); 0);

endend behavioral; behavioral;

0A0A33AA22AA11AA00 0B0B33BB22BB11BB00 0000C0000C00

4-bit adder:4-bit adder:Behavioral Arch. Behavioral Arch.

SpecificationSpecification


Simple combinational function:Simple combinational function: Dataflow description Dataflow description

librarylibrary ieee; ieee;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall;;

entityentity func2 func2 isis portport (x1,x2,x3: (x1,x2,x3: inin std_logic; std_logic; f: f: outout std_logic ); std_logic );endend func2 func2

architecturearchitecture dataflow dataflow ofof func2 func2 isisbeginbegin f <= (f <= (notnot x1 x1 and notand not x2 x2 andand x3) x3) oror (x1 (x1 and notand not x2 x2 and notand not

x3) x3) oror (x1 (x1 and notand not x2 x2 andand x3) x3) oror (x1 (x1 andand x2 x2 and notand not x3); x3);endend logicfunc; logicfunc;


Dataflow: Full AdderDataflow: Full Adderlibrarylibrary ieee; ieee;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall;;

entityentity fulladd fulladd isis portport (Cin, x, y: (Cin, x, y: inin std_logic; std_logic;

s, Cout:s, Cout: outout std_logic); std_logic);endend fulladd; fulladd;


Dataflow: Full Adder (cont.)Dataflow: Full Adder (cont.)architecturearchitecture logicfunc logicfunc ofof fulladd is fulladd isbeginbegin s <= x s <= x xorxor y y xorxor Cin; Cin; Cout <= (x Cout <= (x andand y) y) oror (Cin (Cin andand x) x) oror (Cin (Cin andand y); y);endend logicfunc; logicfunc;


Structural: 4-bit adderStructural: 4-bit adderlibrarylibrary ieee; ieee;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall;;

entityentity adder4 adder4 isis -- s = x+y -- s = x+y portport (Cin: (Cin: inin std_logic; std_logic; x3,x2,x1,x0:x3,x2,x1,x0: inin std_logic; std_logic;

y3,y2,y1,y0:y3,y2,y1,y0: inin std_logic; std_logic; s3,s2,s1,s0:s3,s2,s1,s0: outout std_logic; std_logic; Cout:Cout: outout std_logic ); std_logic );

endend adder4; adder4;


Structural: 4-bit adder Structural: 4-bit adder (cont.)(cont.)

architecturearchitecture structural structural ofof adder4 adder4 isis signalsignal c1,c2,c3: std_logic; c1,c2,c3: std_logic; componentcomponent fulladd fulladd portport (Cin,x,y: (Cin,x,y: inin std_logic; std_logic; s,Cout: s,Cout: outout std_logic); std_logic); endend componentcomponent;;

beginbegin stage0: fulladd stage0: fulladd port mapport map (Cin,x0,y0,s0,c1); (Cin,x0,y0,s0,c1); stage1: fulladd stage1: fulladd port mapport map (c1,x1,y1,s1,c2); (c1,x1,y1,s1,c2); stage2: fulladd stage2: fulladd port mapport map (c2,x2,y2,s2,c3); (c2,x2,y2,s2,c3); stage3: fulladd stage3: fulladd port mapport map

(Cin=>c3,Cout=cout,x=>x3,y=>y3,s=>s3);(Cin=>c3,Cout=cout,x=>x3,y=>y3,s=>s3);endend structural; structural;

Custom orderCustom order

Same order as Same order as declarationdeclaration


2-to-1 MUX2-to-1 MUXlibrarylibrary ieee; ieee;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall;;

entityentity mux2to1 mux2to1 isis portport (d0,d1,s: (d0,d1,s: inin std_logic; std_logic;

y:y: outout std_logic); std_logic);endend mux2to1; mux2to1;

architecturearchitecture behavioral behavioral ofof mux2to1 mux2to1 isisbeginbegin withwith s s selectselect y <= d0 y <= d0 whenwhen ‘0’, ‘0’, d1 d1 when otherswhen others;;endend behavioral; behavioral;


DecoderDecoderlibrarylibrary ieee; ieee;useuse ieee.std_logic_1164. ieee.std_logic_1164.allall;;

entityentity dec2to4 dec2to4 isis portport (w: (w: inin std_logic_vector(1 std_logic_vector(1 downtodownto 0); 0); e:e: inin std_logic; std_logic; y:y: outout std_logic_vector(0 std_logic_vector(0 toto 3)); 3));endend dec2to4; dec2to4;


Decoder (cont.)Decoder (cont.)architecturearchitecture behavioral behavioral ofof dec2to4 dec2to4 isis signalsignal ew: std_logic_vector(2 ew: std_logic_vector(2 downtodownto 0); 0);beginbegin ew <= e & w; -- concatenation!ew <= e & w; -- concatenation! withwith ew ew selectselect y <= “1000” y <= “1000” whenwhen “100”, “100”, “ “0100” 0100” whenwhen “101”, “101”, “ “0010” 0010” whenwhen “110”, “110”, “ “0001” 0001” whenwhen “111”, “111”, “ “0000” 0000” whenwhen othersothers;;endend behavioral; behavioral;

VHDL για Σχεδιασμό Συνδυαστικών Κυκλωμάτων

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Transcript of VHDL για Σχεδιασμό Συνδυαστικών Κυκλωμάτων