VHDL Intro 2005

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An introductory presentation in VHDL

Transcript of VHDL Intro 2005

  • 1 VHDLVHDL

    1-bitFA

    xy

    Cin

    Sum

    Cout

    EE

    A

    B

    sel

    yMUX

    2

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    VHDL

    Very high speed intergrated circuitHardwareDescriptionLanguage

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    VHDL

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    IBM, Texas Instruments Intermetrics VHSIC 1983

    1987 (IEEE 1076-1987)

    1993 (IEEE 1076-1993)

    VHDL 87 VHDL 87

    VHDL 93VHDL 93

    4

    VHDL

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    ""

    ( )(structuralstructural, behavioralbehavioral, dataflowdataflow)

    ,

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    (chip)

    9 ,

    6

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    ;

    9

    9 (Boolean)

    9 VHDL9 K

    9 Functional timing

    9 CPLD FPGA

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    B VHDL

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    (data objects) (data types)

    T (operators)

    -- This is a VHDL comment

    (97 )Begin, for, else, if, end, not, and,

    8

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    std_logic / std_logic_vector K ieee.std_logic_1164

    9 std_logic_vector -bits9 std_logic 1-bit

    std_logic_vector (N-1 downto 0);std_logic_vector (1 to N);

    :

    :

    Signal A : std_logic ; -- A : 1-bit signal

    Signal R : std_logic_vector (7 downto 0) ; -- R : 8-bits signal

    A

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    bit / bit_vector9

    9 bit_vector -bits9 bit 1-bit

    9 ('0' '1') signed / unsigned9 std_logic/std_logic_vector

    ieee.std_logic_signed ieee.std_logic_unsigned

    9 :

    10

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    boolean

    real

    integer :

    Variable count : integer :=2348;

    :

    Variable a : real := 1.0E+2;

    :

    Variable flag : boolean := TRUE;

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    typetype identifier is type_definition :

    :

    type byte is range 0 to 255 ;

    type oct_digit is ('0','1','2','3','4','5','6','7');

    subtypesubtype identifier is subtype_ind range expr1 to expr2 :

    :

    subtype byte is integer range 0 to 255 ;

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    (constants)

    (variables)

    (signals)

    Constant low : std_logic := '0' ;

    Variable cnt : std_logic_vector(2 downto 0) ;

    Signal Cin : std_logic ;

    Constant zero_signal : std_logic_vector(5 downto 0) := "000000" ;

    )) (constant) , (variable)

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    : A

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    VHDL

    and_gate.vhd

    16

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    B ( MAX+plus II Altera) ieeeieee lpmlpm

    alteraaltera

    Library _ ;Use _._.all ;

    :

    9 std_logic_11649 std_logic_unsigned9 std_logic_signed9 std_logic_arith

    9 lpm_components

    9 maxplus29 megacore

    : Library ieee ;Use ieee.std_logic_1164.all ;

  • 917

    O

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    ntity _ is Port ( _ {,_} : mode _ ;

    _ {,_} : mode _);

    End entity _ ;

    :

    (modes) in out buffer inout

    ))

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    O

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    Entity FA isPort ( A, B, Cin : in std_logic ;

    S, Cout : out std_logic );End entity FA ;

    :

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    19

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    rchitecture _ of _o is {Signal }{Constant }{Component }{Function }{Procedure }

    Begin{Port map }{Process }{Generate }{ (concurrent) }

    End architecture _ ;

    :

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    Mo

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    (behavioral)

    (dataflow)

    (structural)9

    (.. )

    9 ( , flip-flops, ..)

    9 (.. )

    9

    9 lean

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    Library ieee;Use ieee.std_logic_1164.all;

    (structural)

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    Entity FA isPort (

    );End entity FA ;

    A, B, Cin : in std_logic;S, Cout : out std_logic

    bit (1-bit FA) 1o :

    22

    x1

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    Library ieee;Use ieee.std_logic_1164.all ;

    (structural)

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    4-bits 2o :

    VHDL :

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    (structural)

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    Entity adder_4bit is Port ( A, B : in std_logic_vector (3 downto 0) ;

    Cin : in std_logic ;S : out std_logic_vector (3 downto 0);

    Cout : out std_logic );End entity adder_4bit ;

    component FA Port ( A, B, Cin : in std_logic;

    S, Cout : out std_logic);end component;

    Architecture arc of adder_4bit is

    Signal C : std_logic_vector (4 downto 0);

    VHDL (.) :

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    (structural)

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    VHDL (.) :

    end arc ;

    Cout

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    Case

    case expression iswhen value1 => statements_1;when value2 => statements_2;when value3 => statements_3;when others => statements_n;

    end case;

    :

    CaseCase process

    ))

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    Begincontrol Y Y Y Y

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    If

    if condition_1 thenstatements_1;

    elsif condition_2 thenstatements_2;

    elsif else

    statements_n;

    end if;

    :

    IfIf process

    ))

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    If

    A B Y0 0 1

    1 0 10 1 1

    1 1 0

    NAND

    Process (A, B)Beginif A /= B then -- A=1 B=0, A=0 B=1

    Y

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    If

    A B Y0 0 1

    1 0 10 1 1

    1 1 0

    NAND

    Process (A, B)Beginif ( (A=B) and A='1' ) then -- A=B='1'

    Y

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    loop (2/3)

    label: while condition loop statements_1;[next [label]] [when condition];[exit [label]] [when condition];

    end loop;

    :

    looploop ))

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    loop (3/3)

    label: for identifier in range loop statements_1;[next [label]] [when condition];[exit [label]] [when condition];

    end loop;

    :

    looploop ))

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    Library ieee;Use ieee.std_logic_1164.all ;Use ieee.std_logic_unsigned.all ;

    (dataflow)

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    4-bits 3o :

    VHDL :

    Entity adder4_dataflow isPort ( Cin : in std_logic ;

    A, B : in std_logic_vector (3 downto 0) ;S : out std_logic_vector(3 downto 0) ;Cout : out std_logic ) ;

    end adder4_dataflow ;

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    (dataflow)

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    VHDL (.) :

    Architecture arc of adder4_dataflow is

    Signal s_temp : std_logic_vector(4 downto 0) ;

    Begins_temp

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    (dataflow)

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    A B Y0 0 1

    1 0 10 1 1

    1 1 0

    NAND

    with control selectY

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    A

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    (clock) falling_edge() rising_edge()

    event

    wait until

    if falling_edge (clock) thenQ

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    A

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    p1: Process (reset, clock)Begin

    if reset = '0' thenQ

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    A

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    8-bits (PIPO) 6o :

    Library ieee ;Use ieee.std_logic_1164.all ;

    Entity register_8bit isPort ( reg_in : in std_logic_vector (7 downto 0) ;

    clock, reset, load : in std_logic ; reg_out : out std_logic_vector (7 downto 0) ) ;

    End entity register_8bit ;

    VHDL :

    44

    A

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    VHDL (.) :

    p1: Process (clock, reset)Begin

    if reset = '1' then reg_out

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    9/ ALU 4-bits ( )

    9 Accumulator ( )

    4

    sel_logic

    A[3:0] B[3:0]

    ALU_sel

    AC_in [3:0]

    ALU

    44

    4

    AC_out [3:0]

    Accumulatorload

    reset

    clock

    Cin

    Cout

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    ALUALU

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    A/ (ALU)

    (accumulator) 4-bits

    9 2--1 4-bits9 4-bits

    (add) (and or)

    ALU:

    48

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    A/ (ALU) ALU.vhd mux2to1_4bit.vhd adder_4bit.vhd

    ALU.vhd accumulator.vhd

    (ALU + ACC) ALU_final.vhd (accumulator) accumulator.vhd

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    2--1 4-bits

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    Library ieee ;Use ieee.std_logic_1164.all ;

    Architecture mux_arc of mux2to1_4bit is

    Entity mux2to1_4bit isPort ( f0, f1 : in std_logic_vector(3 downto 0) ;

    sel : in std_logic ;mux_out : out std_logic_vector(3 downto 0)) ;

    End entity mux2to1_4bit ;

    Beginwith sel select

    mux_out

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    A/ (ALU)

    component adder_4bitPort ( A, B :