Shunt-Peaking (1)gram.eng.uci.edu/faculty/green/public/courses/270c/... · 2016-09-19 · EECS 270C...

EECS 270C / Winter 2013 Prof. M. Green / U.C. Irvine 1

Shunt-Peaking (1)

By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance.


Properties of Shunt-Peaking

€

ωr2

=1

LCL

1−CLR2

L

⎛

⎝ ⎜

⎞

⎠ ⎟

Resonant frequency:

No resonance for

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LCLR2

< 1

CL

X Re s

Im s

L = 0: pole at s = −1/RC

X O

L ≠ 0: zero at s = −R/L additional pole at s ≈ −(1/CR + R/L)

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Z(s) = R ⋅1+ s L

R1+ sCLR + s2LCL

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Z( jω) = R ⋅1+ jω L

R1−ω2LCL( ) + jωCLR

Frequency response:


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L = 0BW = 6.3 GHz

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LCLR2

= 0.3

L = 1.8 nH BW = 9.4 GHz

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LCLR2

= 0.6

L = 3.7 nH BW = 14.3 GHz

Shunt-Peaking -- AC Response

Use of shunt-peaking increases small-signal bandwidth

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CL = 38 fFR = 400 Ω


Shunt Peaking − Transient Response (1)

Step Response:

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L = 0td = 13.4 ps

L = 1.8 nH td = 8.5 ps

L = 3.7 nH td = 6.7 ps

Pulse Response (Δtin = 50 ps):

L = 3.7 nH Δtout = 50.8 ps ISI = 16 mUI

L = 1.8 nH Δtout = 50.0 ps ISI = 0 mUI

L = 0 Δtout = 48.7 ps ISI = 26 mUI


Other Advantages of Shunt-Peaking

•  CML load is passive & linear

•  Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance ⇒ inductors can be placed far away from other CML circuit elements.


long metal lines

Effect of Shunt-Peaking Inductor Parasitics (1)

•  Series resistance RP simply adds to R

•  Shunt capacitance CP resonates with L …

L L

R R

CL CL CL CL

L L

R R

RP RP

CP CP


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LCLR2

= 0

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LCLR2

= 0.3

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LCLR2

= 0.6

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LCLR2

= 0

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LCLR2

= 0.3

€

LCLR2

= 0.6

Moderate amount of parasitic capacitance has similar effect to slightly larger inductor.

Disadvantages of using passive inductors: •  Consume huge die area •  Difficult to design & model

Effect of Shunt-Peaking Inductor Parasitics (2)

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CP = 0

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CP = 0.2CL

ISI (UI) vs. input pulse width

ISI (UI) vs. input pulse width


Multi-layer Inductors (1)

metal 6

metal 5 d

Distance d between two metal layers is much smaller than lateral distances (e.g., w, l, s)

metal 6

metal 5

d


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φ1

φ2

⎛

⎝ ⎜

⎞

⎠ ⎟ =

L1 MM L2

⎡

⎣ ⎢

⎤

⎦ ⎥

i1i2

⎛

⎝ ⎜ ⎞

⎠ ⎟

L1 L2 φ1 φ2

+

_

+

_

i1 i2

2-port representation of coupled inductors:

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M = k L1L2

Passivity constraint: 1≤k

For metal geometries close to each other, k is close to unity.

series connection of coupled inductors:

L1 L2

i1

i2

M

φ1

+

_ φ2

+

_

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φseries =φ1 +φ2 = (L1 + M)i1 + (L2 + M)i2

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iseries = i1 = i 2

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Lseries =φseries

iseries

= L1 + L2 + 2M

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⇒

For L1 = L2 = L, we have:

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Lseries = 2L + 2M = 2L(1+ k) ≈ 4LIn general, for n layers we have:

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Lseries ≈ n2L

Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance.



Ci

Cj

For more details, see:

A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620-628.

€

Leffective ≈ 4L

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Ceffective ≈13

Ci +1

12Cj

Effective Capacitance:



metal 6 only 100µ x 100µ w = 4; s = 2; n = 4 L=2.0 nH R=6.9 Ω

metal 6 over metal 4 46µ x 46µ w = 4; s = 2; n = 2.5 L=2.0 nH R=12.5 Ω

+


Area comparison:


Active Inductors (1)

Rgyr

+

_ v1

i1

+

_

v2

i2

Ideal gyrator:

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v2 = Rgyr i1v1 = −Rgyr i2

Impedance inversion:

Rgyr

+

_ vin

iin

C

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Zin = Rgyr2 sC( )

Port 1 exhibits inductance when port 2 is connected to a capacitance.

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v1v2

⎛

⎝ ⎜

⎞

⎠ ⎟ =

0 −Rgyr

Rgyr 0

⎡

⎣ ⎢

⎤

⎦ ⎥

i1i2

⎛

⎝ ⎜ ⎞

⎠ ⎟

Matrix representation (Z-parameters):



RG

+

_

v1 i1

+

_ v2

i2

i1 applied with port 2 open-circuited:

i2 applied with port 1 open-circuited:

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v2 =1

gm

i1

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v1 = − RG −1

gm

⎛

⎝ ⎜

⎞

⎠ ⎟ i2

(Assume RG gm > 1)

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v1v2

⎛

⎝ ⎜

⎞

⎠ ⎟ =

1 gm − RG −1 gm( )1 gm 1 gm

⎡

⎣ ⎢ ⎢

⎤

⎦ ⎥ ⎥

i1i2

⎛

⎝ ⎜ ⎞

⎠ ⎟

Complete Z-parameters (lossy/active gyrator):

Consider common-drain configuration:


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v1v2

⎛

⎝ ⎜

⎞

⎠ ⎟ =

1 gm 1 gm −RG

1 gm 1 gm

⎡

⎣ ⎢

⎤

⎦ ⎥

i1i2

⎛

⎝ ⎜ ⎞

⎠ ⎟

+

_

vin


Interpretation of non-ideal matrix entries:


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Zsource =1

gm

1+ sCgsRG

1+ sCgs gm

⎡

⎣ ⎢

⎤

⎦ ⎥

At low frequencies (Cgs open) ⇒ Zsource = 1/gm

At high frequencies (Cgs short) ⇒ Zsource = RG


Impedance at port 1 with port 2 terminated with transistor Cgs:


€

ω

€

gm

Cgs

€

1CgsRG

€

1gm

€

RG

€

Zsource

€

Leff ≈CgsRG

gm

=RG

ωT

€

gmRG > 1

Equivalent circuit:

+

_

vin

€

1gm

€

RG −1

gm

€

Cgs ⋅RG

gm



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Av =gm 1

gm 2

=W1

W2

For shunt peaking:

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L ≈ 0.3CLR2

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CgsRG

gm2

= 0.3 CL

gm22

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gm 2RG = 0.3 CL

Cgs

Low-frequency gain:

CML Buffer with Active Inductor Load

€

WL

⎛

⎝ ⎜

⎞

⎠ ⎟ 1

=40.18

€

WL

⎛

⎝ ⎜

⎞

⎠ ⎟

2

=2.50.18

€

ISS = 400µA


Active Inductor AC Response

RG = 4k

RG = 2k

RG = 0


Active Inductor Transient Response (1)

RG = 0 PW = 97ps

RG = 5k PW = 100 ps

RG = 10k PW = 104 ps

Differential signals:


Active Inductor Transient Response (2)

Problem: n-channel load shifts output by Vt. Vsb > 0; body effects exacerbates this effect..

Single-ended input

Single-ended outputs

Single-ended signals:


Alternate topology: p-channel load exhibits lower Vt (Vbs = 0)

Active Inductor Alternate Topology

differential

single-ended

Shunt-Peaking (1)gram.eng.uci.edu/faculty/green/public/courses/270c/... · 2016-09-19 · EECS 270C...

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