Oversampled A/D Conversion · B. A. Wooley – 7 – EE315 Spring 2002 • Integrator accumulates...

B. A. Wooley – 1 – HANDOUT #31EE315

Spring 2002

Oversampled A/D Conversion

Basic concept:

Exchange resolution in time for that in amplitude through the used of oversampling, feedback and digital filtering.

Oversampling Modulators

Predictive

•

∆

Modulation

• DPCM (Differential PCM)

Noise-Shaping

•

Σ∆

Modulation

• Cascaded (Multistage)

Σ∆

Modulation

• Multilevel

Σ∆

Modulation

• Interpolation

OversamplingModulator

DigitalLowpass

Filter

fNw(kMT)x(kT)

fSx(t) y(kT)

fS = 1/T = sampling ratefN = 1/MT = Nyquist rateM = oversampling ratio

B. A. Wooley – 2 – EE315Spring 2002

Benefits of oversampling:

• Relaxed transition band requirements for analog antialiasing (and reconstruction) filters

• Reduced baseband quantization noise power

Antialiasing

fBf

fS 2fS

fBf

x̃ f( )

x f( )

fS = fS(minimum) = 2fB

Input must be band limited priorto sampling

Nyquist Sampling

fB

ffsfs/2

x f( )Antialiasing

Filter

Oversampling

fS > 2fB

Input


Baseband Noise

For an active discrete-time quantizer with step size

∆

and sampling rate f

S

(which is not in overload), the quantization noise power is distributed uniformly across the Nyquist bandwidth.

The power spectral density of the quantization error, e, is

and all of the quantization noise is aliased into the Nyquist band, –f

S

/2 to f

S

/2.

When f

B

= f

S

/2, then the baseband (–f

B

< f < f

B

) quantization noise power is

Ne(f)

fB–fB fS/2–fS / 2

NB

f

Ne f( ) e2

fS------

∆2

12------

1fS-----= =

SB0 Ne f( ) fd

fB–

fB

∫ ∆2

12------= =


When f

B

< f

S

/2, the baseband quantization noise power is

where

= OVERSAMPLING RATIO

2

×

increase in M

⇒

3dB reduction in S

B

⇒

1/2 bit increase in resolution

A much greater improvement in resolution with increasing M can be obtained by embedding the quantizer in a feedback loop.

FEEDBACK can be use for PREDICTION (

∆

modulation) or NOISE SHAPING (

Σ∆

modulation)

In general, noise shaping modulators are more robust and easier to implement than predictive modulators

SB Ne f( ) fd

fB–

fB

∫ ∆2

12------

1fS-----

Ne f( ) fd

fB–

fB

∫= =

SB0

2fB

fS---------

=SB0

M----------=

MfS

2fB---------≡


Delta Modulation

• Quantizes the difference between the input x, and the quantization signal, q

• q is generated by accumulating the quantized differences

• Typically a 1-bit quantizer with a small step size; step size can be adapted to accommodate “slope overload” (signal changing too fast).

• Fundamental practical problem is the accumulation of D/A mismatch error in the demodulator

D/A

Σ–

+x

Quantizer

Integrator

q

y vD/A

MODULATOR DEMODULATOR

∫

∫

1-bitcode


Noise Shaping Modulators

• Sample and coarsely quantize the input at a rate well above the Nyquist rate

• Shape the spectrum of the quantization noise so as to push most of its energy outside the signal baseband

• Out-of-band noise, including quantization noise, is suppressed by a subsequent digital lowpass filter (DECIMATION FILTER)

• Output of the digital filter can be resampled at a lower sampling rate if the filter provides adequate antialiasing, as well as noise suppression

Σ∆ Modulation

Simplest noise-shaping modulator is a first-order Σ∆ (or ∆Σ) modulator with 1-bit quantization

D/A

–

+

QuantizerIntegrator

x(kT)

q(kT)

y(kT) v(kT)

Modulator Demodulator

1-bitcode

∫u(kT)

D/Aw(kT)

–


• Integrator accumulates the difference between the input, x(kT), and the quantization signal, q(kT)

• Feedback keeps the integrator output, w(kT), near zero, thus minimizing the low-frequency difference between x and q

• For 1-bit quantization:

– No D/A nonlinearity

– Quantizer just a comparator

– 2-level D/A converter can be an analog switch network toggling between + and – full scale

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0 50 100 150 200 250

Mo

du

lato

r In

pu

t, Q

uan

tize

r O

utp

ut

Time (t/T)

Σ∆ Modulator Response


Linearized Discrete-Time Model:

In this representation of a “first-order” Σ∆ modulator, the quantization error is modeled as an additive error sequence, e(kT), with the z-transform E(z).

It is not strictly valid to assume the error sequence is random and uncorrelated with the input, especially when a 2-level quantizer is used. For a 2-level quantizer, the quantization error is highly correlated with the modulator input. Nonetheless, the model does illustrate the shaping of the quantization noise spectrum. It does not account for the appearance of strong discrete noise tones in that spectrum.

A(z) as specified above is simply a delaying discrete-time integrator that can be implemented as:

X(z) Y(z)+

–A(z) +–

E(z)

where A z( ) z 1–

1 z 1––

-----------------=

z–1+

Delay


From the above model it follows that

∴

∴

where

(first-order difference)

Thus, in the output Y(z), the quantization error is filtered by the first-order difference HE(z)

In the frequency domain

where

T = 1/fS

Y z( ) A z( ) X z( ) Y z( )–[ ] E z( )+=

Y z( ) A z( )1 A z( )+---------------------- X z( ) 1

1 A z( )+---------------------- E z( )+=

1 A z( )+ 1 z 1–

1 z 1––

-----------------+ 1

1 z 1––

-----------------= =

A z( )1 A z( )+----------------------

z 1–

1 z 1––

-----------------

1 z 1––( ) z 1–

= =

Y z( ) z 1– X z( ) HE z( )E z( )+=

HE z( ) 1 z 1––=

HE jω( ) 1 e jωT––( ) 2e jωT 2⁄– ejωT 2⁄ e j– ωT 2⁄

–2

------------------------------------------- = =

2e jωT 2⁄– j ωT 2⁄( )sin[ ]=

2e jωT 2⁄–( ) e jπ 2⁄–( ) ωT 2⁄( )sin[ ]=

2 ωT 2⁄( )sin[ ] e j ωT π–( ) 2⁄–=


Thus,

If Ne(f) is the power spectral density of the quantization error e(kT), the spectral power density of the quantization noise in the modulator output is:

HE f( ) 2 ωT2

-------- sin 2 2πfT

2-------------

sin= =

2 πfT( )sin= 2 πf fS⁄( )sin=

Ny f( ) HE f( ) 2Ne f( )=

First-Order Noise Shaping

Ideal DigitalLowpass Filter

FrequencyfB fN fS/2

No

ise

Sh

apin

g F

un

ctio

n

Noise Shaping


If it is assumed that the spectrum of the quantization error is white, which is not actually the case, and if SQ denotes the quantization error power,

then

and the baseband quantization noise power in the modulator output is

If f << fS = 1/T, then

and

SQ e2≡ ∆2

12------=

Ne f( )SQ

fS-------

∆2

12------

1fS-----= =

SB NY f( ) fd

fB–

fB

∫ HE f( ) 2Ne f( ) fd

fB–

fB

∫= =

SQ

fS------- 2 πfT( )sin[ ] 2 fd

fB–

fB

∫=

πfT( ) πfT≅sin π f fS⁄( )=

SB 4SQ

fS-------

π ffS-----

2fd

fB–

fB

∫≅ 4π2 SQ

fS3

------- f3

3----

fB–

fB

=

4π2 SQ

fS3

------- 2fB

3

3---------

=π2

3------

2fB

fS---------

3SQ=


∴

Since a full-scale sinusoid has an amplitude of at most ∆/2, the maximum dynamic range of the modulator is

Each 2× increase in M results in a 9dB in dynamic range, which corresponds to 1.5 bits of resolution

Because of the spectral tones that result from the correlation of the quantization error with the input, the dynamic range of a first-order Σ∆ modulator with 1-bit quantization is not as large as this result indicates

SBπ2

3------ 1

M-----

3SQ≅ π2

3------ 1

M-----

3 ∆2

12------

=

DR 10 ∆ 2⁄( )2 2⁄SB

--------------------------log=

10 ∆2 8⁄

π2

3------ 1

M-----

3 ∆2

12------

---------------------------------log= 10 9

2π2---------M3log=

10 9

2π2--------- 30 M( )log+log=


Error Compensation Model of a Σ∆ Modulator

Configuration of original patent on Σ∆ modulation (Cutler, U.S. Patent 2,927,962, 3/8/60); referred to as a transmitting terminal using error compensation

∴

Thus, this topology provides first-order noise shaping. However, it is difficult to implement.

The error compensation topology can be rearranged as follows to obtain the conventional first-order Σ∆ modulator.

Predictor

Quantizer

+xn

DELAY

+

εn

yn+

qn

yn xn qn– εn+=

qn εn 1–=

yn xn εn εn 1––+=

Y z( ) X z( ) 1 z 1––( )E z( )+=


First, the delay is moved in to the forward path:

This configuration implements the noise-differencing relationship with a delay of the input:

Next, simply rearrange the paths at the input and output of the quantizer to obtain the conventional first-order Σ∆ modulator

+xn

+

εn

yn+

qn

DELAY

yn xn 1– εn εn 1––+=

Y z( ) z 1– X z( ) 1 z 1––( )E z( )+=

+xn

εn

yn+

qn

DELAY+

IntegratorQuantizer


Oversampling A/D Conversion

Combine an oversampling noise-shaping modulator with a low-pass digital filter that removes the out-of-band quantization noise. The digital filter also provides the antialiasing need to allow resampling at a lower sampling rate (“decimation”).

Higher-Order Σ∆ Modulators

• Single quantizer

Multi-loop noise differencing

Single-loop with multi-order filter

• Cascaded (multistage)

ANALOGIN

DIGITALOUT

OVERSAMPLINGMODULATOR

DECIMATIONFILTER

f /Msfs

f = Sampling Rate

M = Oversampling Ratio

s


Single-Quantizer Modulator

X(z) Y(z)+

–A(z) +–

F(z)

E(z)

Y z( ) HX z( )X z( ) HE z( )E z( )+=

HX z( ) A z( )1 A z( )F z( )+----------------------------------=

HE z( ) 11 A z( )F z( )+----------------------------------=

A z( )HX z( )HE z( )---------------=

F z( )1 HE z( )–

HX z( )-------------------------=


Noise Differencing Modulators

Class of modulators for which

That is

and

Noise differencing modulators can be implemented with a single quantizer and L nested loops. However, limit cycle instability occurs for L > 2.

For an Lth order noise differencing modulator

The quantization noise is thus shaped as

Y z( ) z n– X z( ) 1 z 1––( )

LE z( )+=

HX z( ) z n–= HE z( ) 1 z 1–

–( )L

=

HE z( ) 1 z 1––( )

L=

HE f( ) 2 πf fS⁄( )sin L=

Ny f( ) HE f( ) 2Ne f( ) 2 πf fS⁄( )sin[ ] 2LNe f( )= =

L=3

L=2

L=1

Ideal DigitalLowpass Filter

FrequencyfB fN fS/2

No

ise

Sh

apin

g F

un

ctio

n, |

HE(f

)|


Baseband Quantization Noise

As in the case of the first-order modulator, if it is assumed that the quantization noise is white with a uniform spectral density SQ/fS, then the quantization noise remaining in the baseband of the output is

If f << fS = 1/T, then

and

Thus, for an Lth order modulator, every doubling of M results in an increase in dynamic range of 6L+3 dB (L+0.5 bits)

SB NY f( ) fd

fB–

fB

∫ HE f( ) 2Ne f( ) fd

fB–

fB

∫= =

SQ

fS------- 2 πfT( )sin[ ] 2L fd

fB–

fB

∫=

πfT( ) πfT≅sin π f fS⁄( )=

SB 22L SQ

fS-------

π ffS-----

2Lfd

fB–

fB

∫ 22Lπ2L SQ

fS2L 1+

--------------- f2L 1+

2L 1+-----------------

fB–

fB

= =

22Lπ2L SQ

fS2L 1+

--------------- 2fB

2L 1+

2L 1+-------------------

=π2L

2L 1+-----------------

2fB

fS---------

2L 1+

SQ=

π2L

2L 1+-----------------

1M-----

2L 1+SQ=


Noise differencing modulators can be implemented with a single quantizer and L nested loops. However, limit cycle instability occurs for L > 2. Thus, we consider the case where a single quantizer is used with L = 1 and L = 2:

For HX(z) = 1

L = 1: HE(z) = (1– z–1) ⇒

L = 2: HE(z) = (1– z–1)2 ⇒

≠ 1

0

20

40

60

80

100

120

Dyn

amic

Ran

ge

(dB

)

4 8 16 32 64 128 256 5120

Oversampling Ratio, M

L=1

L=2

L=3

Res

olu

tio

n (

Bit

s)

4

8

16

12

20

A z( ) z 1–

1 z 1––

-----------------=

F z( ) 1=

A z( ) z 1–

1 z 1––( )

2-------------------------=

F z( ) 2 z 1––=


A canonical realization of a 2nd-order noise-differencing modulator is thus:

which can be rearranged as

X Y+

––

F(z)

z–1+

z–1

+

z–1

A(z)

+

+

–+

–

E

X Y+

–– z–1+

z–1

+

z–1

+

+ –+

–

+

––

z–1

E


The above topology reduces to

Thus, the classical topology for a 2nd-order Σ∆ modulator is

The first integrator in this configuration is nondelaying. Such an integrator can be realized using a delaying integrator identical to that used in the second stage with the following configuration.

X Y+

–– z–1+

z–1

+ ++

––

E

Σ–

+

(nT)x (nT)yA/D

D/A

QUANTIZER

Σ+

+

DELAY

Σ–

+INTEGRATOR 1

Σ+

+DELAY

INTEGRATOR 2

q(nT)

Y(z) = z–1 X(z) + (1 –z–1)2

E(z)


which can be rearranged as:

To eliminate the multiply by 2:

(nT)x (nT)yA/D

D/A

QUANTIZER

DELAY

INTEGRATOR 2

DELAY+

INTEGRATOR 1

Σ+

q(nT)

+Σ

–

+Σ

+

+Σ

–

+Σ

+

(nT)x (nT)yA/D

D/A

QUANTIZER

DELAY

INTEGRATOR 1

DELAY

INTEGRATOR 2

2

q(nT)

+Σ

–

+Σ

+Σ

–

+Σ

+

+

(nT)x (nT)y

D/A

DELAY 212

INTEGRATOR 1

Σ+

+DELAY

INTEGRATOR 2

q(nT)

A/D

QUANTIZER

+Σ

–Σ

+

+Σ

–


The gain of 2 preceding the second integrator stage results in the need for a large dynamic range at the output of this stage, in turn requiring a signal swing at the input that is well below the supply voltage.

However, if a 2-level quantizer is used, then the “gain” preceding the second stage can be adjusted arbitrarily. In that case, the second stage can be implemented using the same topology as the first stage.

Second-Order Σ∆ Modulator (w/ 2-level quantizer)

Integrator Dynamic Range

(nT)x (nT)yA/D

D/A

QUANTIZER

DELAY12

INTEGRATOR 1

DELAY

INTEGRATOR 2

12

q(nT)

+Σ

–

+Σ

+

+Σ

–

+Σ

+

-1 -0.5 0 0.5 1

Den

sity

Integrator 1 Output/∆

Traditional Modulator

Modified Modulator

-2 -1 0 1 2

Den

sity

Integrator 2 Output/∆


Integrator Gain

Integrator model:

Sensitivity of baseband noise to integrator gain:

go

Po

+ z–1 y(kT)x(kT)

DelayClippingGain

Leak

Integrator Gain, g0

-2

-1

0

1

2

3

4

5

0.3 0.4 0.5 0.6 0.7 0.8

Rel

ativ

e B

aseb

and

Err

or

(dB

)

Input Power = – 40 dB


Integrator leak

Integrator “leak” refers to the finite dc gain of a practical integrator

+Σ

+H (z) =

1–P0

z -1z -1

P

DELAY

0

AM

PL

ITU

DE

(d

B)

H ⇔

LOG FREQUENCY

0

-1

0

1

2

3

4

5

0 0.5 1 1.5 2

Rel

ativ

e B

aseb

and

Err

or

(dB

)

Analytical Result

Simulation (Input Power = –20 dB)

M/H0


Integrator Linearity

with nonlinearity

v(kT + T) = u(kT) + α1[u(kT)]2 + α2[u(kT)]3 + . . .

+ v(kT) + β1[v(kT)]2 + β2[v(kT)]3 + . . .

DELAY+

Ideal Integrator

u(kT) v(kT)

v(kT + T) = u(kT) + v(kT)

70

75

80

85

90

95

100

105

-30 -25 -20 -15 -10 -5 0

TS

NR

(d

B)

Input Level (dB)

Ideal ModulatorSimulationAnalytical Result

σ1 = β1 = 0.01, 0.02, 0.05, 0.1%


70

75

80

85

90

95

100

105

-30 -25 -20 -15 -10 -5 0

TS

NR

[d

B]

Input Level [dB]

σ2 = β

2 = 0.05, 0.2, 1.0%

Ideal ModulatorSimulationAnalytical Result


Integrator Slewing

Integrator Slewing

u(kT)

kT

v(kT)

DELAY

STEP RESPONSE

v(kT)

v(kT)

kT

STEP RESPONSE

C2

u(kT)

C1

-v(kT)

-5

0

5

10

15

20

25

30

35

0.9 0.95 1 1.05 1.1 1.15 1.2

Rel

ativ

e B

aseb

and

Err

or

(dB

)

Slew Rate (∆/T)

Noise + Distortion

Noise

Input Power = – 5 dB


Comparator Hysteresis

1-bit A/D vu

u

v

Hysteresis, h∆

-5

0

5

10

15

20

Rel

ativ

e B

aseb

and

Err

or

(dB

) Simulation (Input Power = –20 dB)

Analytical Result

Hysteresis, h10-2 10-1 100


Analog Integration

Two basic circuit approaches to realizing analog integrators in a CMOS technology are CONTINUOUS TIME and SAMPLED-DATA

Continuous Time Integration

• gm-C

• MOSFET-C

Sampled-Data Integration

• Switched-Current

• Switched-Capacitor

Continuous-Time Integrators

Limitations

• Integrator output is sensitive to timing jitter

• Sensitive to waveform asymmetry

e.g. response to ...011000... differs from response to ...010100...

• Waveform asymmetry can enhance spurious noise tones

• Frequency response of loop governed by capacitors and MOS transconductance or resistance

• Poor linearity

−

+

CI

Vi VoA

Vtune

MR

−

+

Vi Vogm

Vtune

CI

MOSFET - C gm - C


Switched-Current Integrator

Limitations

• Current sources must be cascode to reduce output conductance ==> high supply voltage

• Large Vgs – VT needed to reduce sensitivity to VT mismatch ==> high power dissipation

• Sensitive to switch parasitics and charge injection

2I kI

VDD

Iin

Iout

Φ1 Φ1 Φ2

M1 M2 M3 = k × M2

Cgs2Cgs1 Cgs3

Iout

Iin--------- kz 1–

1 z 1––

-----------------=


Switched-Capacitor Integrator

Fully-differential switched-C integrator

• Common-mode input and output levels can beset independently

−

+

CI

CSΦ1 Φ2

Φ1Φ2Vout

Vin

Vout

Vin-----------

CS

CI------- z 1–

1 z 1––

-----------------

=

CICS

Vcmi Vout

+

−

Φ1

Φ1

Φ1

Φ1

Φ2

+

− +

−

CIΦ2CS

Vcm,in

Φ2

Φ2

Vin

+

−

Vcmo


CMOS Implementation of a 2nd-Order Σ∆ Modulator

Timing Diagram

UT

1

1 4

1

1

N

C

C

C

C

V ref

+

V ref

–

V ref

+

V ref

–

Vre

f+

Vre

f–

Vre

f+

Vre

f–

1

t

t

t

thase 1 Phase 2


Phase 1

OUT

S1

S1

S1

S1

S3

S3S4

S4

IN

C1

C1

C2

C2

• Sample inputs

• Compare outputs

S3

S3

S4

S4

C1

C1

C2

C2

OUT

S1

S1

S1

S1

S3

S3

S4

S4

IN

C1

C1

C2

C2

• S3 opens before S1

S3

S4

S4

C1

C1

C2

C2

S3


Phase 2

UT

S

S

S

S

S2

4

C

C

C C

Vre

f+

Vre

f–

Vre

f+

Vre

f–

Vre

f+

Vre

f–

Vre

f+

Vre

f–

C

• Enable feedback• Integrate• Reset comparator

UT

2S2

2

Vre

f+

Vre

f–

Vre

f+

Vre

f–

V ref

+

V ref

–

V ref

+

V ref

–

S4 opens before S2


Operational Amplifier Requirements

• Linear settling ⇒ high slew rate

• High speed ⇒ single-stage amplifier

• Low distortion ⇒ gain > 60dB

• Wide dynamic range ⇒ low noise and large output swing

• Differential architecture

Class AB Op Amp

I bias I bias

VDD

MC2

MC4

VOUT–

Bias 2

Bias 4

MC1

MC3

VOUT+

Bias 1

Bias 3

VIN –VIN+

I1 I2


Common-mode biasing:

Comparator

V D

MO

MPLIFIER CORE

MOUT–OUT+

7 5

3 1 Mbias1

Mbias2

2

2

2

6 C8

2 C4Mbias1

Mbias2

B2

φ φ

φ φ

φ φ

φ φ

φ φ

φ φ

OUT

OUT

φ

+

–

VI1

VI2

M9 M3 M4 M10

M5 M6

M7 M1 M2 M8


Summary of Measured Performance

Dynamic Range 98 dB (16 bits)

Peak SNDR 94 dB (0.002% THD)

Nyquist rate 50 kHz

Sampling rate 12.8 MHz

Oversampling Ratio 256

Differential input range 4 V

Supply voltage 5 V

Supply rejection 60 dB

Power dissipation 13.8 mW

Active Area 0.39 mm2

Technology 1-µm CMOS

Measured SNDR

0

10

20

30

40

50

60

70

80

90

100

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0

SN

DR

(d

B)

Input Level (dB)

Signal Freq. = 2.8 kHzClock Freq. = 12.8 MHzM = 2560 dB = 4V

p-p


Baseband Spectrum

Subcircuit Performance

Operational Amplifier

DC gain 67 dB

Unity-gain frequency 50 MHz

Slew rate 350 V/µsec

Linear output range 6 V

Sampling rate 12.8 MHz

Integrator

Settling time constant 7.25 nsec

Comparator

Offset 13 mV

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

0 2 4 6 8 10 12 14 16 18 20 22 24

Po

wer

Sp

ectr

al D

ensi

ty (

dB

)

Frequency (kHz)

–5 dB, 2.8 kHz Input

Measured

Ideal


Integrator Step Response

Attributes of 2nd-order Σ∆ modulator:

• Simple architecture

• Very tolerant of component mismatch

• Stable operation

• High linearity

• Small area, low power

-0.5

0

0.5

1

1.5

2

2.5

0 10 20 30 40 50

Dif

fere

nti

al O

utp

ut

Vo

ltag

e (V

)

Time (nS)

Measured

Simulated


Quantization Noise Spectra of Σ∆ Modulators

Owing to the correlation of the quantization error with the input in oversampling modulator employing a single quantizer, discrete noise peaks (tones) appear in the output spectrum for certain inputs.

The following simple example illustrates the origin of the noise tones:

(kT):

(kT):

• x(kT) = (0.001) ∆/2

• x(kT) = 0 (Midrange Input)

⇒ No Low Frequency Component

⇒ Frequency Component in Baseband

000 T

• • •

• • •


For a single-quantizer modulator, the quantizer error is defined as the difference between the analog input and output of the quantizer:

System analysis (R. Gray, “Spectral Analysis of Sigma-Delta Quantization Noise) of an ideal first-order Σ∆ modulator indicates that the spectrum of the quantizer noise is not white. For a dc input, xdc, the spectrum consists solely of impulses with power

at frequencies

where k is a nonzero integer and represents the fractional part of w.

The strongest tones occur for small values of k because of the reciprocal dependence in the expression for Se(k).

The power in the quantization noise tone in the output of the modulator that corresponds to Se(k) is

+Σ FILTER A/D

D/A

QUANTIZER

–

q(kT)

u(kT)y(kT)x(kT)

e(kT) = q(kT) – u(kT)

Se k( ) ∆2

2πk( )2------------------=

fk kxdc

∆--------- 1

2---+

⟨ ⟩ fS=

w⟨ ⟩

Sy k( )∆2 πfkT( )sin[ ] 2

πk( )2-----------------------------------------=


Quantization noise spectrum for a first-order modulator:

Discrete tone in a 2nd-order modulator spectrum:

0

0.1

0.2

0.3

0.4

0.5

0 0.1 0.2 0.3 0.4 0.5

-26-24-22-20-18-16-14-12

0 0.1 0.2 0.3 0.4 0.5DC Input Level x/∆

MS

E (

dB

)F

req

uen

cy f

k/f s

-140

-120

-100

-80

-60

-40

-20

0

0 2 4 6 8 10 12 14 16 18 20 22 24

Po

wer

Sp

ectr

al D

ensi

ty (

dB

)

Frequency (kHz)


Quantization noise spectra for M = 256:

Noise spectrum of 2nd-order modulator:

Max

imu

m P

eak

(dB

)

-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-120

-110

-100-90

-80-70

-60

-50

k: 2 5 3 4 5 1

First-Order Σ∆ Modulator

-80

-90

-100

-110

-120

Second-Order Σ∆ Modulator

DC Input Level (∆)

Max

imu

m P

eak

(dB

)

-80

-90

-100

-110

-120

-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5DC Input (∆)

-80

-90

-100

-110

-120

-3 dB Input

Measured

Simulated


Tones near midrange in 2nd-order modulator:

Worst tone a 2nd-order modulator:

-120

-115

-110

-105

-100

-95

-90

-0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016

-120

-115

-110

-105

-100

-95

-90

-0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016DC Input (∆)

Max

imu

m N

ois

e P

eak

(dB

) Measured

Simulated

-140

-130

-120

-110

-100

-90

0 5 10 15 20 25

Measured

-140

-130

-120

-110

-100

-90

0 5 10 15 20 25Frequency (kHz)

Simulated

Po

wer

Sp

ectr

al D

ensi

ty (

dB

)


Composite spectra for several DC inputs:

Worst-tones as a function of oversampling ratio:

-140

-130

-120

-110

-100

-90

0 5 10 15 20 25

Po

wer

Sp

ectr

al D

ensi

ty (

dB

)

Frequency (kHz)

E

E

E

E

E

E

E

E

E

E

E

E

D

D

D

D

D

DI

I

I

I

I

I

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

Wo

rst-

Cas

e T

on

e (d

B)

E Simulated

D Equation (5.4)

I Measured

Oversampling Ratio

8 16 32 64 128 256 512 1024

1st-order Σ∆

2nd-order Σ∆


Spectra for a sinusoidal input:

Spectral tones in a single-quantizer, 4th-order Σ∆ modulator:

-140

-120

-100

-80

-60

-40

-20

0

0 10 20 30 40 50

Po

wer

Sp

ectr

al D

ensi

ty (

dB

)

Frequency (kHz)

Second-Order Noise Shaping

-200

-180

-160

-140

-120

-100

-80

0 5 10 15 20 25

Sp

ectr

al P

ow

er (

dB

)

Frequency (kHz)


Approaches to “whitening” the error spectrum

• Cascaded sigma-delta modulation

• Multibit quantizers

• Dither

Simulation Requirements

The design of oversampling data converters requires a behavioral simulation capability because of the need to simulate long data traces.

The results presented here were obtained using the program MIDAS, a functional simulator for mixed digital and analog sampled data systems.

MIDAS

• System described by netlist

• Simulate in discrete time

• Includes tools for performance analyses such as spectral analysis, distortion and statistical functions

• Flexible I/O, including interface to test environment

• Written in C++

• User extensible with C-like code

• Not an “expert” tool for novice designers; intended for use by designers who understand what models should be used or constructed

Oversampled A/D Conversion · B. A. Wooley – 7 – EE315 Spring 2002 • Integrator accumulates...

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Transcript of Oversampled A/D Conversion · B. A. Wooley – 7 – EE315 Spring 2002 • Integrator accumulates...