A 5.3mW, 2.4GHz ESD Protected Low-Noise Amplifierin a 0.13μm RFCMOS Technology

Davide Brandano, Manuel Delgado-Restituto, Jesús Ruiz-Amaya and Angel Rodríguez-VázquezInstituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC)

Edif.CICA-CNM, Avda. Reina Mercedes s/n, 41012 - Sevilla, SPAIN Phone: +34 955 05 6666, Fax: +34 955 05 6686, E-mails: [brandano|mandel|ruiz|angel]@imse.cnm.es

Abstract—An Electrostatic Discharge (ESD) protected Low-Noise Amplifier (LNA) for the 2.4GHz ISM band designed in a0.13μm standard RFCMOS technology is presented. The ampli-fier, including packaging effects, achieves 16.8dB power gain,reflexion coeffcients S11, S22 < -30dB over the 2.4GHz ISM band,a peak noise figure of 1.8 dB, and an IIP3 of 1dBm, while draw-ing less than 4.5mA dc biasing current from the 1.2V power sup-ply. Further, the LNA withstands a Human Body Model (HBM)ESD stress up to ±2.0kV, by means of the additional custom pro-tection circuitry.

Index Terms—LNA, Electrostatic discharge (ESD) protection,Noise figure, RF CMOS.

I. INTRODUCTION

This paper presents the design of a 1.2V CMOS LNA, im-plemented in a 0.13μm RF process, for short range commu-nications in the 2.4GHz unlicensed ISM (Industrial,Scientific and Medical) band, as defined by the standardsBluetooth, IEEE 802.11b/g or IEEE 802.15.4. The amplifieruses an inductively degenerated common-source topologyand includes pads with ESD protection for reliability reasons.The influence on the amplifier performance of the parasiticsfrom the ESD protection circuit, input and output pads, bond-wires and package leads has been considered during design.The LNA achieves 16.8dB power gain with an input match ofS11<-30dB over the ISM band, a peak noise figure lower than1.8 dB, and an IIP3 of 1dBm, while drawing less than 4.5mAdc biasing current. Additionally, the protection circuits at theRF pads provide HBM ESD withstand voltages of ±2.0kV.

The paper is organized as follows. In Section II, detailson the design of the LNA are given. Section III describes theESD protection circuitry and its influence on the LNA per-formance. Section IV summarizes the main characteristics ofthe amplifier, obtained from electrical simulations of theextracted layout. Finally, Section V gives some conclusions.

II. LNA DESIGN

Fig.1 shows a simplified schematic of the designedCMOS LNA. It uses an inductively degenerated common-source cascoded topology, in which the source inductance is

implemented by five paralleled low-loss bond wires. Fig.2(a)shows the equivalent small-signal circuit for the input stageof the LNA. The off-chip L-type network composed by and is designed to match a known source impedance to a smaller resistance value, , at the resonance frequency,

1. Sizing of and must also consider the parasiticsof the selected QFN package. The inductance contributed bythe series gate bondwire is represented by and de-notes the sum of the parasitic capacitances due to the pad,

, and the ESD protection circuit, . The integratedspiral coil has been modelled by an inductance in serieswith a resistance which accounts with its ohmic losses.The common source transistor M0 of Fig.1 has a transcon-ductance , a gate-to-source capacitance and a gate re-sistance . The impedance at the drain of M0 is assumed tobe negligible small by the effect of the cascode transistor M1.Also it is assumed that the Miller effect arising from the gate-

1. If is sufficiently large compared to the of the LNA inputdevice, the impedance level at the LNA input becomes too low to bematched 50Ω only by employing a series inductance [1], [2]. For thisreason, similar to other designs [2], the input impedance level of theproposed LNA exhibits a value lower than 50Ω (about 20Ω).

Lead-frame

Pad with ESDprotection

Off-chipmatchingnetwork

M0

M1

MB

Bondwire

Pad

Figure 1. Schematic of the packaged LNA circuit with ESD Protection.

DecCap

5X14

14x5

x4

x5

Lm

Cm

LgLbw

Ld

+Lead-parasitics

Off-chipmatchingnetwork

+Lead-parasitics

MCL

CmLm Rs

Rpω0 Cm Lm

Cp Cgs

Lbw Cp

CPAD CESDLg

Rg

gm Cgsrg

1-4244-1342-7/07/$25.00 ©2007 IEEE 72

to-drain capacitance of M0 can be ignored. Finally, represents the degenerative source inductance, implementedby five paralleled bondwires – therefore, . Due tothe low loss of the bondwires, no parasitic resistance is con-sidered.

The impedance seen at the left of the reference plane of Fig.2(a) can be written as , where

and are given by,

(1)

where it is assumed that the impedance at the reference plane is purely resistive with resistance,

(2)

Combining with the integrated inductor and the parasiticresistances at the gate of M0, the simplified schematic ofFig.2(b) is obtained where

(3)

From Fig.2(b), the power matching condition at the input ofthe LNA can be found to be [3],

(4)

where denotes the cut-off angular frequency of the tran-sistor. Note that since for the 0.13μm process is high, alow value of is required for input matching – this justifies

the use of five bondwires in parallel. On the other hand, theresonance condition at the input stage of the LNA reads as[3]-[5],

(5)

which can be recursively solved to obtain in terms of (in this design, is set to 2.44Ghz).

Taking advantage of the equivalent simplified schematicof Fig.2(a) and Fig.2(b), the magnitude of the output current

of the input stage can be calculated, making use (4) and(5), as

(6)

which can be written as

(7)

where is given by Eq. (8), at the bottomof this page. Using (7), the transconductance of the LNA in-put stage is given by,

(9)

and the LNA voltage gain at the nominal operation frequencyby

(10)

where is the impedance of the LC resonator circuitat the drain of M1 (see Fig.1). In the proposed design, the in-ductance of this tank circuit has been optimized to maximizethe voltage gain of the LNA. Then, the capacitance has beentuned so that the tank resonates at the nominal operation fre-quency.

Fig.3 depicts a small-signal circuit for the noise analysisof the proposed LNA. In this circuit, represents the noisepower contribution of the source, is the noise contribu-

Cgd Ls

Ls Lbw 5⁄≈

Figure 2. (a) Small-signal circuit for the input stage of the LNA. (b) Equivalent simplified schematic.

Ls

Cgs

CpCm

Lbw Rg rg+

gmvgsvin

iout

Zin

Lg

LmRs

Rm

Ls

Lg eq, CgsRg eq,

gmvgs

iout

vp

(a)

(b)

1 2

Zp

Zp2 Req jω0Leq+ Req

Leq

ReqRm

ω02Cp

2Rm2 1 ω0

2CpLbw–( )2+--------------------------------------------------------------------=

LeqLbw Cp ω0

2Lbw2 Rm

2+( )–ω0

2Cp2Rm

2 1 ω02CpLbw–( )2+

--------------------------------------------------------------------=

1

RmRs

1 ω0CmRs( )2+-------------------------------------=

Zp

Rg eq, Req Rg rg Req≈+ +=

Lg eq, Leq Lg+=

Rg eq,gmLsCgs

------------ ωTLs≡≈

ωTωT

Ls

ω01

Lg eq, Ls+( )Cgs

------------------------------------------=

Lg ω0f0

iout

iout gm vgsgm vp

2jω0Rg eq, Cgs------------------------------------- vp

2jω0Ls-----------------= = =

ioutvin

2ω0Ls---------------ζ Rs Lbw Cp Cm, , ,( )=

ζ Rs Lbw Cp Cm, , ,( )

Gmioutvin--------

ζ Rs Lbw Cp Cm, , ,( )2ω0Ls

----------------------------------------------= =

Av Gm Zd jω0( )=

Zd jω0( )

Cp

Lg

L rg

Ls

Cgs

gmvgs

iout

id2ig

2

vrg

2

Figure 3. Small Signal Circuit for Noise Figure Analysis of the proposed LNA with ESD Protection

vRg

2Rs

vs2

Rg

Cm

vs2

vRg

2

(8)ζ Rs Lbw Cp Cm, , ,( ) ω02 1

ω0------ ω0Cm Lbw CpRsRm–( )–⎝ ⎠⎛ ⎞ 2

ω02CmLbwRsCp CpRm RsCm+ +( )2+

⎩ ⎭⎨ ⎬⎧ ⎫ 1–

ξω0------≡=

73

tion from the ohmic losses of the integrated coil, is thenoise power due to the gate parasitic resistance of transistorM0, is the noise contribution of its channel and the under-neath substrate resistance , and is the gate-inducedcurrent noise power. For the sake of simplicity, the noise con-tribution from the cascode stage has been neglected – it haslow impact on the overall noise performance of the LNA. As-suming perfect power matching, the noise power contribu-tions from the above sources to the LNA output current, canbe calculated at the resonance frequency,

(11)

where and , , and are bias dependentparameters [3]. If the parasitic losses of the tank circuit at thedrain of M1 are modelled by a parallel resistor at the fre-quency operation, its noise contribution to the LNA outputnoise current is,

(12)

From (11)- (12), the noise factor of the LNA is found by add-ing up the different noise power contributions (taking into ac-count the correlation between the drain and gate-inducednoise contributions [4]), and normalizing by the noise currentdue to . This gives,

(13)

where and is the correlation coefficient

of the gate and drain noise sources [3].

III. ESD PROTECTION CIRCUITRY DESIGN In the LNA, the input and output terminals have been

ESD-protected by means of dual-diode arrays as shown inFig.1 [5]. Each array consists of 5 rows and 14 columns of di-odes. Major issues on the design of this protection circuit

have been the added shunt capacitance, , and the toler-able ESD current.

At RF, capacitance becomes a low impedance paththat will short the signal to ground, thus affecting the powergain and the noise figure of the LNA. Additionally, ESD pro-tection structures, being extra devices to the circuit core, willcause noise coupling to the substrate through . There-fore, must be reduced as much as possible. In this de-sign, the ratio is about 0.4 and the total shuntcapacitance of the protection circuit is , givingan overall parasitic capacitance , including bondpads effects.

Reducing the shunt capacitance runs against the need tosustain large ESD currents, as this improves with the size ofthe diodes. In this design, the sizing of diode arrays has beenaccomplished by exciting the LNA with HBM discharges asdefined by the standard MIL-STD-883G [6]. As an example,Fig.4 shows the discharge current and the gate voltage of M0when the LNA is stressed by a +2kV HBM signal. The break-down voltage for this transistor is 2.7V, higher than the peakvoltage at the gate of M0. Similar tests have been also appliedfor negative peak values and other voltages ranging from0.5kV to 2kV. Table 1 summarizes the HBM ESD character-istics of the LNA, indicating the different satisfied classes.

Together with the ESD protections, a low on-resistancegrounded gate NMOS (ggNMOS) device, in the Fig. 1,is used for power clamping the supply node.

IV. LNA PERFORMANCE

Fig.5 shows the layout of the LNA which occupies andarea of 0.7mm2, including pads, in a 0.13μm CMOS technol-ogy. The size of the input device M0 was chosen according to

vrg

2

id2

Rsub ig2

in Rs,2 Gm

2 vs2

4------------- Gm

2 kBTRs= =

in Rg,2 kBTRggm

2

ω02Cgs

2 Rg eq, Rg ωTLs+ +( )2--------------------------------------------------------------------=

in rg,2 kBTrggm

2

ω02Cgs

2 Rg eq, rg ωTLs+ +( )2-------------------------------------------------------------------=

in d,2 γ

α---kBTgm kBTgmbs

2 Rsub+=

in g,2 1 gmω0Ls( )2+

ω0Ls( )2------------------------------------

kBTαδ5gm

-----------------⋅=

gmbs ηgm= η α δ γ

Rd

in Rd,2 4kBT Rd⁄=

Rs

F 1Rg eq,

2

Rsξ2

-------------ω0ωT------⎝ ⎠⎛ ⎞

2 4ωT2 Rg

Rg eq, Rg ωTLs+ +( )2--------------------------------------------------- …++≈

4ωT

2 rg

Rg eq, rg ωTLs+ +( )2-------------------------------------------------- γ

α---ω0

2gmΨ …+ + +

ω02gmbs

2 Rsub

1Gm

2 RdRs

--------------------+ +

Ψ 1 2c δ5γ----- α2δ

5γ---------+ += c

5.999 5.9995 6 6.0005 6.001 6.0015 6.002 6.0025 6.003 6.0035 6.004

x 10-3

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Dis

char

ge C

urre

nt [A

]

5.999 5.9995 6 6.0005 6.001 6.0015 6.002 6.0025 6.003 6.0035 6.004

x 10-3

-1

-0.5

0

0.5

1

1.5

2

M0

Gat

e Vo

ltage

[V]

time [sec]

2000V HBM TEST

M0 GATE VOLTAGE

HBMDISCHARGECURRENT

Figure 4. Discharge Current and Breakdown Voltage from 2kV HBM Test

CESD

CESD

CESDCESD

CESD Cgs⁄CESD 95fF=

Cp 240fF=

TABLE 1. Human Body Model Tests

HBM Voltage level Peak Current Rise Time Decay Time SatisfiedClass

500 V 315 mA 3.5 ns 150 ns Class Ib1000 V 622 mA 2.5 ns 160 ns Class Ic2000 V 1280 mA 2.5 ns 160 ns Class II

MCL

74

[3] and employs a finger structure to reduce as much as pos-sible its gate resistance. The size of M1 has been chosen to bethe same as M0 and, in the layout, they have been placed nextto each other [2]. This choice adequately reduces the Millereffect and also facilitates merging of the drain of M0 andsource of M1, reducing the cascode node capacitance. Criticalnodes of the circuit (including input and output pads) havebeen shielded from the substrate by metal plates to ground –this prevents the parasitic substrate resistance from degradingthe . The layout includes metal-sandwich decoupling ca-pacitors between the power supply and ground to stabilize theLNA biasing.

Figs.6-7 have been obtained using electrical simulationsfrom extracted layout, including foundry-provided estima-tions of the package parasitics and bondwire electrical char-acteristics. The input and output terminals of the LNA havebeen 50Ω matched with reflection coefficients S11 < -30dBand S22 = -30dB over the 2.4GHz ISM band. The measuredpower gain of the amplifier is shown in Fig.6. The gain has apeak value of 16.8dB at 2.46GHz and remains above 16.5dBover the ISM band. Fig.7 shows the noise figure of the LNA,revealing that it remains around 1.8dB in the band of interest.The proposed LNA achieves a reverse isolation value lowerthan -29dB and a stability factor of about 1.8. Finally, as Fig.8shows, the achieved IIP3 is 1dBm, obtained by a two-tone testwith 2MHz beat frequency in the 2.4GHz ISM band.

V. CONCLUSIONS

A 1.2V 2.4GHz 0.13μm CMOS LNA has been presented.The LNA is HBM ESD-protected ±2.0kV and achieves lessthan 1.8dB noise figure. The circuit uses 15 pins of a QFN24package and occupies 0.7mm2. The current consumption ofthe LNA is about 4.4mA and obtains almost 17dB powergain.

ACKNOWLEDGMENTS

This work has been supported by the TIC2003-02355 andthe TEC2006-03022 Projects.

REFERENCES

[1] P. Sivonen and A. Pärssinen, “Analysis and Optimization of Packaged Inductively Degenera-tion Common-Source Low-Noise Amplifier With ESD Protection,” IEEE Trans. On Micro-wave Theory and Techniques, vol. 53, No. 4, pp. 1304-1313, Apr.2005.

[2] V. Chandrasekhar, C. M. Hung, Y. C. Ho, and K. Mayaram, "A packaged 2.4 GHz LNA in a0.15um CMOS process with 2kV HBM ESD protection," presented at the 28th European Sol-id-State Circuits Conference, 2002 (ESSCIRC 2002).

[3] T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits (2nd Edition),” Cam-bridge University Press, Cambridge (UK), 2004.

[4] J. Janssens and M. Steyaert, “CMOS Cellular Receiver Front-Ends, from Specification to Re-alization,” Kluwer Academic Publisher, Dordrecht (The Netherlands), 2002.

[5] P. Leroux and M. Steyaert, “LNA-ESD Co-Design for Fully Integrated CMOS Wireless Re-ceivers”, Springer, Dordrecht (The Netherlands), 2005.

[6] Department of Defense, ”MIL-std-883g Test Method Standard - Microcircuits,” Feb. 2006.Figure 5. Layout of the LNA.

NF

Figure 6. Power Gain.

1 1.5 2 2.5 3 3.5 4

x 109

0

2

4

6

8

10

12

14

16

18

[dB

]

Frequency [Hz]

Power Gain

1 1.5 2 2.5 3 3.5 4

x 109

1

2

3

4

5

6

7

8

[dB

]

Frequency [Hz]

Noise Figure

-30 -25 -20 -15 -10 -5 0 5-80

-60

-40

-20

0

20

40

Input Power [dBm]

Out

put P

ower

[dB

m]

3rd Order Input Referred Intercept Point

1dB/dB

1st Order Harmonic

3dB/dB

3rd Order Harmonic

Figure 7. Noise Figure.

Figure 8. Two-Tone IIP3 measure.

75