Development of a 2MS/s 12-bit SAR ADC with Calibration for operation in LAr … · 2018. 11....

Development of a 2MS/s 12-bit SAR ADC with Calibration for operation in LAr TPC

FEE 2018

May 21, 2018

Yuan Mei

1YUAN MEI [email protected]

Outline

• Overview

• Calibration Method

• Architecture

• Simulation Results

• Conclusion


SAR ADC

5/21/2018 Yuan Mei

PipelineSAR

Flash

ΔΣ

3

Basic SAR Architecture

• Binary search algorithm → N cycles for N bits

• Linearity of SAR ADC is limited by the DAC mismatch error

• DAC calibration improves ADC linearity (using advanced search algorithm)

DAC SAR Logic

Vin

Digital Outputs

Comparator


Calibration Method


• An alternative approach for SAR ADC is to introduce decision redundancy

• Redundancy is introduced by insert extra steps and helps relax the DAC settling accuracy during MSBs operation

• Redundancy making searching range overlapping which enable DAC mismatch calibration in the digital domain

Choice of redundancy steps


• Based on the σ (standard deviation of the capacitor mismatch) provided by the foundry. Two extra redundancy steps are needed [1].

• Redundancy is building directly into the DAC, leading to a sub-radix-2 approach

• A total of 14 conversion steps are required to obtain a 12bits resolution

Capacitor weights using redundancy


Conventional SAR ADC This Work12 bits-cycles to convert 12 bits

14 bits-cycles to convert 12 bits

Number of bit-cycling Bit Weight Bit Weight Redundant range (LSBs)

1 (MSB) 2048 1920 2562 1024 1024 1283 512 544 644 256 288 325 128 144 326 64 80 167 32 40 168 16 24 89 8 12 810 4 8 411 2 6 412 1 2 213 214 1

Capacitor Mismatch Calibration Algorithm

• LMS algorithm to update weight of capacitor

• Each sampled analog signal will be digitized twice

Notes:

LMS: Least-mean square algorithmWi represents the respective bit weight. µi is the step size of the update equation and is scaled according to the bit. e[N] is the total error of the Nth step. The dN are the raw ADC output;Δd are digitized offset of the inserting analog offset Δa 8YUAN MEI [email protected]

SARCORE

Encode 1

Encode 2

e[n]

LMS

d

a a

2

D1

D2 d2

d1

doutVin

W1

W2

Calibration engineLMS : Wk [N+1] = Wk[n] - µ*e[n]*dk[n]

e [N] = d1[n] - d1[n] -2 d

Fig. Block diagram of the perturbation based digital calibration for SAR ADC [3]

Timing Diagram of the proposed digital calibration


40 Cycles

Reset

Sample

Output1

D14 D13 D12 D2 D1

Clk

Output2

D14b D2b D1b

Input regeneration

Simulations by applying digital calibration

• Simulations are done in Cadence @ 77K temperature

• All blocks are implemented and simulated in transistor level

• Unit capacitor is MIM cap provided by foundry (about 10 fF)

• DAC mismatch errors are the major error source


Capacitor mismatch calibration verification

Weights (Unit Cap)-Original

Weights (Unit Cap)-With mismatch errors

1920 1926

1024 1028

544 538

288 286

144 142

80 81

40 41

24 23

12 11

8 8

6 5

2 3

2 1

1 1

• Set random mismatch on capacitor weights

• Simulate to see if calibration can find the optimal weight and improve the performance


Capacitor mismatch calibration simulation results (1/3)

Ideal Real After

calibration

W1

(MSB)

1920 1926 1925

W2 1024 1028 1027

W3 544 538 537.7

W4 288 286 285.8

X-axis: # of samples Y-axis: Capacitor weight

Simulated with 2^14 (16,384) samples, weights are converged around 10,000 samples



Ideal Real After

calibration

W5 144 142 141.9

W6 80 81 80.95

W7 40 41 40.97

W8 24 23 22.98

X-axis: # of samples Y-axis: Capacitor weight13YUAN MEI [email protected]


Ideal Real After

calibration

W9 12 11 10.98

W10 8 8 8.07

W11 6 5 5.05

W12 2 3 3.04

Y-axis: Capacitor weightX-axis: # of samples

With calibration, we updated all the weights in the DAC.

14

With CalibrationENOB= 11.2 bits

Without CalibrationENOB = 8.3 bits

Dynamic test simulation before and after calibration (Pre-sim)FFT points:2^14

• ENOB is improved• Dynamic range also improved


Consider only errors are capacitor mismatch

With CalibrationENOB= 11.9 bits

Without CalibrationENOB = 8.3 bits

Dynamic test simulation before and after calibration (Ideal)FFT points:2^17

• ENOB is further improved from 11.2bits to 11.9bits

• Dynamic range also improved from 69.1 dB to 73.6dB 16YUAN MEI [email protected]

Consider only errors are capacitor mismatch

With more samples :

Static test simulation before and after calibration

• Linearity is improved with the digital calibration

17

No missing codes!A lot missing codes!

Without Calibration With Calibration

Sample points:2^14

Comparison with theoretical Static test

• Linearity is also improved with more samples

18

With samples 16,384 (2^14) With samples 131,072 (2^17)

19

Neg_CapacitorArray

SAR Logic

Clock Generator

Bootstrap Switch

Neg_Switches

Pos_Switches

Control

Control

Comparator

200 MHZ Clk

40 MHZ Clk

Output Data<D1:D14>

CalibrationEngine by MATLAB

Top_Plate Switches

Bootstrap Switch

Pos_CapacitorArray

NegativeDAC

PostiveDAC

ADC Core Per Channel

Vin_pos Vref_pos Vref_neg

Vin_neg Vref_pos Vref_neg

Vcm

YUAN MEI [email protected]

20

N-DAC

P-DAC

DummyDummy Dummy

Dummy Dummy Dummy

Du

mm

yD

um

my

Du

mm

yD

um

my

Dummy Dummy

Dummy Dummy Dummy

N-DAC DC Switches

P-DAC DC Switches

VCMSwitch

VCMSwitch

Vin+ BootstrapSwitch

Vin- BootstrapSwitch

Comparator

Preamp

Preamp

NomalModeSAR

Logic

CalibrationModeSAR

Logic

Clock GeneratorData Formatter

+LVDS I/O

Digital DomainAnalog Domain

YUAN MEI [email protected]

Floorplan

YUAN MEI [email protected] 21

Size: 3200µm x 320µm

SAR ADC Layout (Single Channel)

Block Name Power consumption 2MS/s

Digital 240 µw

Analog 280 µW

Total 520 µW

22

Power consumption @77K (Post Layout Simulation, R+C+CC)

23

Reference work [3] This study (Post-Sim)

Technology 130 nm 65 nm

Resolution 12 bits 12 bits

Work temperature 300 K 77 K

Power supply 1.2 v 1.2 v

Signal Swing 2.4 Vpp 2.4 Vpp

Sampling Rate 37 MS/s 2 MS/s

SNDR 70.3 dB 72.2 dB

SFDR 81.1 dB 80.9 dB

ENOB 11.39 bits 11.67 bits

INL N/A N/A

DNL N/A N/A

Power consumption 7 mW 0.52 mW

Summary of Performance

Notes:This study used the digital calibration method in the work by W. Liu

W. Liu, JSSC 08/11 [3]

• We have fabricated a synchronized 12 bits SAR ADC in TMSC 65nm process on May 9th.

• The prototype employs the perturbation based calibration to digitally correct the capacitor mismatch error from the DAC

• The SAR ADC core area is 1.02mm2 and consumes about 520 µW at 77K with sampling rate 2MS/s

YUAN MEI [email protected] 24

Conclusion

[1] W. Liu, ‘’Low-Power High-Performance SAR ADC Design with Digital Calibration Technique”, UIUC PHD Thesis, 2010.

[2] C. C. Liu, C. H. Kuo and Y. Z. Lin, "A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS," in IEEE J. of Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, Nov. 2015.

[3] W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE J. of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011.

25

Reference

Backup

• Convergence of Error

5/21/2018 26

Development of a 2MS/s 12-bit SAR ADC with Calibration for operation in LAr … · 2018. 11....

Documents

Transcript of Development of a 2MS/s 12-bit SAR ADC with Calibration for operation in LAr … · 2018. 11....