DD Obsolete - pSemi · PDF file Insertion Loss (dBm)-40C +25C +85C Figure 9. Output Return...
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Page 1 of 13
Document No. 70-0251-05 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
The PE43501 is a HaRP™-enhanced, high linearity, 5-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 7.75 dB attenuation range in 0.25 dB steps. The Peregrine 50Ω RF DSA provides a serial-addressable CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with VDD due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. The PE43501 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS.
Product Specification
50 Ω RF Digital Attenuator 5-bit, 7.75 dB, 9 kHz - 6.0 GHz Product Description
Figure 2. Functional Schematic Diagram
PE43501
Features • HaRP™-enhanced UltraCMOS™ device
• Attenuation: 0.25 dB steps to 7.75 dB
• High Linearity: Typical +58 dBm IP3 • Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast switch settling time
• Programming Modes:
• Direct Parallel • Latched Parallel • Serial-Addressable: Program up to
eight addresses 000 - 111
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
• No DC blocking capacitors required
• Packaged in a 32-lead 5x5x0.85 mm QFN
Figure 1. Package Type 32-lead 5x5x0.85 mm QFN Package
Control Logic Interface
RF Input RF Output
Switched Attenuator Array
Serial In
LE
CLK
A0 A1 A2
Parallel Control 5
P/S
Ob so
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification PE43501
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1 2 3 4 5 6 7 8
Attenuation Setting (dB)
A tte
nu at
io n
Er ro
r (d
B )
200 MHz 900 MHz 1800 MHz 2200 MHZ 3000 MHz 4000 MHz 5000 MHz 6000 MHz
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1000 2000 3000 4000 5000 6000
Frequency (MHz)
B it
Er ro
r ( dB
)
0.25dB State 0.5dB State 1dB State 2dB State 4dB State 7.75dB State
-0.25
0.00
0.25
0.50
0.75
1.00
0 1 2 3 4 5 6 7 8
Attenuation Setting (dB)
S te
p E
rr or
(d B)
200 MHz 900 MHz 1800 MHz 2200 MHz 3000 MHz 4000 MHz 5000 MHz 6000 MHz
1 2 3 4 5 6 70 8
1
2
3
4
5
6
7
0
8
Attenuation State
A tte
nu at
io n
d B
Attenuation
900 MHz 1800 MHz 2200 MHz 3000 MHz 5400 MHz 5800 MHz
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V Parameter Test Conditions Frequency Min Typical Max Units
Frequency Range 9 kHz 6 GHz
Attenuation Range 0.25 dB Step 0 – 7.75 dB
Insertion Loss 9 kHz ≤ 6 GHz 2.3 2.8 dB
Attenuation Error
0 dB - 7.75 dB Attenuation settings 0dB to 3.5 dB Attenuation Settings 3.75 dB to 7.75 dB Attenuation Settings 0dB to 7.75dB Attenuation Settings
9 kHz < 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz
±(0.15+4%) +0.2+4% +0.3+4% -0.2 - 4%
dB dB dB dB
Return Loss 9 kHz - 6 GHz 18 dB
Relative Phase All States 9 kHz - 6 GHz 9 deg
P1dB (note 1) Input 20 MHz - 6 GHz 30 32 dBm
IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 6 GHz 58 dBm
Typical Spurious Value 1 MHz -110 dBm
Video Feed Through 10 mVpp
Switching Time 50% CTRL to 10% / 90% RF 650 ns
RF Trise/Tfall 10% / 90% RF 400 ns
Settling Time RF settled to within 0.05 dB of final value RBW = 5 MHz, Averaging ON. 4 µs
Figure 3. 0.25 dB Step Error vs. Frequency*
Figure 5. 0.25 dB Major State Bit Error
Performance Plots
Figure 4. 0.25dB Attenuation vs. Attenuation State
*Monotonicity is held so long as Step-Error does not cross below -0.25
Figure 6. 0.25 dB Attenuation Error vs. Frequency
Note: 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 3.
Ob so
let e
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification PE43501
Page 3 of 13
Document No. 70-0251-05 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
-70
-60
-50
-40
-30
-20
-10
0
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
R et
ur n
Lo ss
(d B
)
-40C 25C 85C
-60
-50
-40
-30
-20
-10
0
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
R et
ur n
Lo ss
(d B
)
-40C 25C 85C
-60
-50
-40
-30
-20
-10
0
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
R et
ur n
Lo ss
(d B)
0dB 0.25dB 0.5dB 1dB 2dB 4dB 7.75dB
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
R et
ur n
Lo ss
(d B
)
0dB 0.25dB 0.5dB 1dB 2dB 4dB 7.75dB
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0 1 2 3 4 5 6 7 8 9 Frequency (GHz)
In se
rti on
L os
s (d
B m
)
-40C +25C +85C
Figure 9. Output Return Loss vs. Attenuation: T = +25C
Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenuation: T = +25C
Figure 10. Input Return Loss vs. Temperature: 7.75 dB State
Figure 11. Output Return Loss vs. Temperature: 7.75 dB State
Figure 12. Relative Phase vs. Frequency
0
2
4
6
8
10
12
14
16
0 1 2 3 4 5 6 7 8
Frequency (GHz)
Re la
tiv e
P ha
se E
rr or
(D eg
)
0dB 0.25dB 0.5dB 1dB 2dB 4dB 7.75dB
Ob so
let e
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification PE43501
Page 4 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
30
35
40
45
50
55
60
65
70
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)
In pu
t I P
3 (d
B m
)
0dB 0.25dB 0.5dB 1dB 2dB 4dB
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1 2 3 4 5 6 7 8
Attenuation Setting (dB)
A tte
nu at
io n
Er ro
r (d
B )
+25C -40C +85C
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1 2 3 4 5 6 7 8
Attenuation Setting (dB)
A tte
nu at
io n
E rr
or (d
B )
+25 C -40C +85C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-40 -20 0 20 40 60 80
Temperature (Deg. C)
Ph as
e (D
eg )
900 MHz 1800 MHz 3000 MHz
Figure 15. Attenuation Error vs. Attenuation Setting: 1800 MHz
Figure 13. Relative Phase vs. Temperature: 7.75 dB State
Figure 14. Attenuation Error vs. Attenuation Setting: 900 MHz
Figure 16. Attenuation Error vs. Attenuation Setting: 3000 MHz
Figure 17. Input IP3 vs. Frequency
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1 2 3 4 5 6 7 8
Attenuation Setting (dB)
A tt
en ua
tio n
Er ro
r ( dB
)
+25C -40C +85C
Ob so
let e
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification PE43501
Page 5 of 13
Document No. 70-0251-05 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Figure 18. Pin Configuration (Top View)
8
7
6
5
4
3
2
1 24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
161514131211109
Exposed Solder pa
