Dai Testing Seminar 2006-posted - Auburn University

Foster Dai, April, 2006 1

1.1. An An MIMO Multimode WLAN RFIC

2. A 2. A ∆Σ∆Σ Direct Digital Synthesizer ICDirect Digital Synthesizer IC

Foster Dai

VLSI Design & Test Seminar, April 19, 2006

RFIC Design for Wireless Communications


An MIMO Multimode WLAN RFIC

1. 1. An Overview of MIMO TechnologyAn Overview of MIMO Technology

2. 2. MIMO Transceiver DesignMIMO Transceiver Design

3. 3. Transceiver Building Block CircuitsTransceiver Building Block Circuits

4. 4. Measured ResultsMeasured Results

1. Dave G. Rahn, Mark S. Cavin, Foster F. Dai, Neric Fong, Richard Griffith, Jose Macedo, David Moore, John W. M. Rogers, and Mike Toner, “A Fully Integrated Multi-Band MIMO WLAN Transceiver RFIC,” IEEE Journal on Solid State Circuits, Vol. 40, No. 8, pp. 1629-1641, August, 2005. IEEE Symposium on VLSI Circuits, pp. 290 – 293, Kyoto, Japan, June, 2005.


250

200

150

100

50

0-10 10 30-5 0 20 25

Average SNR (dB)/Antenna

Ave

rage

Dat

a R

ate

(Mbp

s)

5 15 35

1x1 1x2 – SD4x4 CBF 4x4 VCBF

16.5dB

Advantages of MIMO Technology

• MIMO can extend range and higher data rates • Graph shows that for a 4X4 MIMO system 16.5dB less S/N ratio required for 54MBit/sec compared to standard technology• As well vector CBF is shown which uses four orthogonal data streams to increase data rate 4X. • VCBF not implemented here (not backwards compatible), but shows future of this technology.


MIMO Transceiver Design

LO Porting Trace

Master Chip

Slave Chip

LO Porting Trace

Transmitting Radio

Beam Forming in the TX to get antenna gain through signal shaping

Master Chip

Slave Chip

Maximum ratioCombining at receive of signals in four paths at the RX

Link

Receiving Radio

Note: Both beam forming and maximum ratio combining controlled by DSP

Two RadiosOn the same chip


MIMO Transceiver Design Issues

MIMO transceiver RFIC design is a challenge due to the followingissues:

1. Multiple radios on same die cause interference, especially PAscause VCO injection-locking. Careful floor planning and proper isolation in layout are critical. VCOs operate at different frequencies from the PAs.

2. All LOs must be synchronized. MIMO calibration requires loop back measurement to match phase and amplitude of all paths.

3. Tx-Tx isolation must be high to maximize the gain from CBF. 30dB or higher desired.

4. Rx-Rx isolation must be maximized in order to maximize the gain from MCR. 40dB desired.


MIMO Transceiver Design Block Diagram

• Uses walking IF architecture for only one synthesizer• Includes 2 a/b/g paths on each chip. • Either master or slave PLL mode. • BB filters switched so same Si used in Tx and Rx.

LNA

PA

RFLO

IFLOQ

IFMIXBBLPF

IFMIX

IFLOI

IFLOQ

VGA

VGARFMIX

PPA

RFOUT1 2.5GHz

RFIN1 2.5GHz

BBI1

BBQ1

RFLO÷4

IFLOI

IFLOQ

∆ΣSYN

VCO RCLPF

XTAL

RFLO÷4

IFLOI

IFLOQ

∆ΣSYN

VCO RCLPF

XTAL

LNARFMIX

RFIN1 5GHz

PARFOUT1 5GHz

Switch

Switch

PPA

LNA

PA

RFLO

IFLOQ

IFMIXBBLPF

IFMIX

IFLOI

IFLOQ

VGA

VGARFMIX

PPA

RFOUT2 2.5GHz

RFIN2 2.5GHzBBI2

BBQ2LNARFMIX

RFIN2 5GHz

PA

RFOUT2 5GHz

Switch

Switch

PPA Path2

Path1

Serial to Parallel Interface

Legend:MatchingNetwork


+

÷4

∆Σ accumulator size F

::

nth order ∆Σ

Fine tune frequency word K

Course tune frequency word C +

Multi-modulusDivider

Referencesource

FRef

÷R PFDChargePump

FRF

VCOs

n

1

off chipLPF

FIF

90°

0°

Reset

Bi-Directional LO Porting Circuit

From master or to slave chip

LO + Reset Signal

RF mixer

IF mixers

BasebandI-Q output

BasebandI-Q input

RF mixer

Multiple InputMultiple OutputTransceiver

Additional Radio Paths (not shown)

Synthesizer Design


Synthesizer

MIMO Transceiver

∆Σ

VCO

MMDPFD/CP

LO

Po

rting

RX

1a

RX

2a

RX

1b/g

RX

2b/g

SPI

IF1 IF2

BB1 BB2

TX

1b/g

TX

2b/g

TX

1a

TX

2a

Chip Layout

• Designed in a 50GHz SiGe BiCMOS technology

• Chip measures 5.4mmX5.4mm

• Placed in a 72pin leadless plastic chip carrier (LPCC) package .

Foster Dai, April, 2006 9Center: 5.18GHzRBW: 11.9344kHz

-110dBm

10dB

/div

-10dBm

B: Ch1 Spectrum Range: -15dBm

Span: 36MHzTimeLen: 320.0304uSec

-2.715RBW: 312.5kHz

2.7152TimeLen: 60 Sym

-1.5

1.5

I-Q

300m

/div

A: Ch1 OFDM Meas Range: -15dBm

EVM Measurements

Shows typical EVM measurement which complies with IEEE 802.11a standard.


Synthesizer Phase Noise Measurements

•Shows good agreement with measured results.

Frequency Offset (kHz)0.1 1.0 10 100 1000 10000

Pha

se N

oise

(dB

c /H

z)-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160


SUMMARY OF TRANSCEIVER PERFORMANCE Parameter Performance

Band 802.11b/g 802.11a

Technology 0.5µm SiGe BiCMOS Voltage Supply 2.75V 2.75V TX Chain Current Supply (1path/2paths)

240/ 400mA

255/ 430mA

RX Chain Current Supply (1path/2paths)

195/ 320mA

195/ 320mA

Synthesizer Current supply

36mA 36mA

TX output power 11dBm 13.5dBm EVM at TX output power

4% (g only) 4%

TX Path to Path Isolation (measured at the PA outputs)

> 40dB > 40dB

RX NF @ Max Gain 4.1dB 7.5dB

RX chain Max Gain 77 dB 72 dB

RX chain Min Gain 5.5dB 25dB

Rx IIP3 @ Min Gain +8.8 dBm -12.8 dBm

RX I/Q Amplitude Imbalance

0.3 dB 0.3 dB

RX I/Q Quadrature Error

2.0° 2.0°

SUMMARY OF TRANSCEIVER PERFORMANCE

Parameter Performance

Band 802.11b/g 802.11aRx Path to Path Isolation (measured at the BB filter output)

>50dB > 40dB

Max DC offset without correction (measured at the output of the BBfilter)

90mV 90mV

Synthesizer Integrated Noise 100Hz to 10MHz

0.35~0.43°rms

0.63~0.86°rms

VCO Phase Noise -120dBc/Hz @ 1MHz

-120dBc/Hz @ 1MHz

In Band Phase Noise -98dBc/Hz @ 10kHz

-98dBc/Hz @ 10kHz

Synthesizer Reference Frequency

40MHz

Synthesizer Step Size 468.75kHz 781.25kHz

Synthesizer Spurious <-50 dBc

Chip Measurements


A Multi-Band Σ∆ Fractional-N Frequency Synthesizer

John W.M. Rogers, Foster F. Dai, Mark S. Cavin, and Dave G. Rahn, “A Fully Integrated Multi-Band SD Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC,”IEEE Journal on Solid State Circuits, Vol. 40, No. 3, pp. 678-689, March, 2005.


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TELECOMM.

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CONFER ENCE

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RECEPTION

12

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1x1 1x2sel 4CBFx2sel 4x2 CBF

AP

Scale: 10feet

Demo of Range Improvement Using the MIMO Transceiver RFIC

Shows improved range of MIMO radios in an office building at 2.4GHz. 4X4 link range too large to show.


• Implemented an IEEE 802.11a/b/g transceiver RFIC for 2.4GHz

and 5.2GHz and Japan 4.9GHz multi-band MIMO WLAN

applications.

• Transceiver RFIC includes two complete radio paths fully

integrated on the same chip.

• Using walking IF architecture, uses a single Σ∆ fractional-N

synthesizer for LO generation.

• Using two RFICs, 4X4 MIMO radio link has been tested under a

typical indoor WLAN environment.

• The measured 4X4 MIMO radio achieves 15dB of link margin

improvement over a conventional SISO radio.

Conclusions


A CMOS Direct Digital Frequency Synthesizer with Single-Stage SD Interpolator and Current-Steering DAC

• DDS spurs and quantization noise due to phase truncation.

• Frequency domain and phase domain Σ∆ noise shaping schemes.

• 12-bit current-steering DAC with Q2 random walk switching scheme.

1.Foster F. Dai, Weining Ni, Yin Shi and Richard C. Jaeger, “A Direct Digital Frequency Synthesizer with Single-Stage ∆Σ Interpolator and Current-Steering DAC,” IEEE Journal on Solid State Circuits, Vol. 41, No. 4, pp.839-850, April 2006. IEEE Symposium on VLSI Circuits, pp. 56–59, Kyoto, Japan, June, 2005.


Conventional ROM-Based DDS

Fine step size requires a large accumulator and a large ROM. To reduce ROM size, the phase word is truncated, causing spurs at DDS output.

+

Z-1

N

N

ND

DAC ~~~

DeglitchLPF

P D-bitsDAC

Filtered sinwaveform

Digitized sinamplitude

Sampled sinwaveform

Phase toamplitudeconversion

Truncatedphase

Phase

Phaseaccumulator

Frequencycontrol word

(FCW)

Phase truncation

MS

B

LSB N-P

2P p

hase

add

ress

es

SINlook up table

D amplitude bitsNumerically controlled oscillator (NCO)

Nclko

FCWff

2=

of


DDS Pros and Cons

• AdvantagesFine frequency tuning resolutionFast frequency switchingQuadrature outputs with accurate I/Q matchingDirect modulations (PSK, FSK, MSK, PM, and FM)Compatible with digital CMOS processing

• DisadvantagesLow output frequencyQuantization noise and spurious tones


Z-1

Phase word

truncation

1-(1-Z-1)k

SINROM

16 168 MSBs

8 LSBs

phaseerror ep(i)

SINword12

12-bitDAC

DAC

DeglitchLPF

SINoutput

Phaseword

4th order Σ∆noise shaper

+ +FCW

DDS With 4th Order Σ∆ Modulator

Implemented in 0.35µm CMOS Technology

• Using a 4th order Σ∆ modulator, ROM sized is reduced by a factor of 16 times, without compressing the ROM.

• ROM size can be further reduced using ROM compression algorithms.


Output Spectrum Before Deglitch Filter

For DDS With 4th Order ∆Σ Modulator

(a) Simulated (b) Measured


With ∆Σ∆Σ Without ∆Σ∆Σ

SFDR improved by 14 dB

72dB 58dB

Comparison of Measured Output Spectrafor DDS with and without The 4th Order ∆Σ Modulator


Die Photo of The ∆Σ DDS Prototype

Implemented in 0.35µm CMOS Technology

Die area = 2.2×2mm2

DDS core = 1.11mm2

Σ∆ accumulator = 0.3×0.2mm2

ROM = 0.3×0.3mm2

ROM size is greatly reduceddue to the use of Σ∆.

DAC = 0.6×1.6mm2

Power consumption = 200mWDAC = 82 mWVdd = 3.3VMax clock frequency = 300MHz


Questions?

Contact Foster Dai

Associate ProfessorDepartment of Electrical & Computer Engineering

200 Broun Hall, Auburn University, Auburn, AL 36849-5201 Phone: (334) 844-1863, Fax: (334) 844-1809, [email protected]

Dai Testing Seminar 2006-posted - Auburn University

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