• date post

07-Mar-2016
• Category

## Documents

• view

247

2

Embed Size (px)

description

Assignment

### Transcript of Basic electronics

• BASIC ELECTRONICS

ASSIGNMENT-II

TRANSISTORS:

1. A BJT has alpha 0.99 and collector-to-base reverse sat current 3A. If emitter current is 10mA, calculate the collector

and base currents.

2. An npn transistor has collector current 4mA and base current 15A. Calculate the alpha and beta values of the

transistor, neglecting the reverse sat current ICBO.

3. In a transistor, 99% of the carriers injected into the base cross over to the collector region. If collector current is

4mA and collector leakage current is 6A, Calculate emitter and base currents.

4. A Ge Transistor has collector current of 40mA when the base current is 0.3mA. If = 125, then what is its collector

cutoff current ICEO?

5. In a transistor circuit, when the base current is increased from 0.32mA to 0.48mA, the emitter current increases from

15mA to 20mA. Find ac and ac values.

6. For a fixed bias circuit using Si transistor, RB = 600k, RC = 3k, VCC = 15V, ICBO = 20 A and = 70. Find the

collector current ICQ and VCEQ at Q-point. Take VBE as 0.7 V.

7. For a fixed bias circuit, VCC = 12 V and RC = 4k. The Ge transistor used is characterized by = 50, ICEO = 0 and

VCE sat = 0.2 V. Find the value of RB that just results in saturation.

8. A three-stage amplifier circuit has first stage gain of 45 dB, second stage gain of 50 dB and third stage gain of 5 dB.

What is the overall gain? If input to the first stage is 0.1mV, what is the output of final stage?

9. An amplifier has maximum gain of 200 and bandwidth of 500 kHz. If lower cutoff freq is 50 Hz, what is the upper

cutoff freq and gain at this frequency?

OPERATIONAL AMPLIFIERS:

1. Design a adder circuit using Op-Amp to give the output: V0 = - (3V1 + 4V2 + 5V3). Use RF = 100K.

2. Design an inverting amplifier using Op-Amp for following specifications:

input voltage=30mV, R1=2k, Rf=15K.

3. A signal source with 2.2 V rms voltage to be amplified to 10 V rms with a phase shift of 1800. Design a suitable op-

amp circuit.

4. In the op-amp integrator circuit if R1CF = 1Sec and input is 2V from 0 to 4 Sec and 0V for all other values,

determine the output voltage and sketch it.

5. Consider a Schmitt trigger circuit with R1 = 50K, R2 = 100 and input voltage peak to peak 5V sinusoidal signal.

Calculate UTP and LTP, assuming saturation voltages to be 15V.

6. Determine the output voltage of an op-amp for input voltages of Vi1 = 200 V, Vi2 = 140 V. the amplifier has a

differential gain of Ad=6000 and the value of CMRR is:

a. 200

b. 105