Printed Electronics: Device Production, Characterisation ...

Printed Electronics: Device Production, Printed Electronics: Device Production, Characterisation and SimulationCharacterisation and Simulation

D. M . TaylorSchool of Electronic Engineering

Bangor UniversityDean Street, Bangor, Gwynedd LL57 1UT, UK

IeMRC Meeting, Loughborough19th March 2012

1

Roll-to-roll Vacuum-processedCarbon Based Electronics

(RoVaCBE)

DALMATIAN TECHNOLOGY

Outline of PresentationOutline of Presentation

Fabrication/characterisation of vacuum-prepared TFTs

Parameter extraction with Silvaco UTMOST 4

Inverter characteristics

Circuit simulation with Silvaco Gateway

Conclusions

Evaporation zone 5 × 10-4 mbar

Winding zone

Unwind

Selective Metallising

Process Drum

Rewind

Anilox Roller and Oil Boiler Cliché Plate

Magnification x 200

Magnification x 60

Magnification x 200

50 μm lines,

gap 80 μm

REGISTRATION ACCURACY

MD: 500 micron

TD: 500 micron

PRINTING RESOLUTION

MD: 30-50 micron

TD: 30-50 micron

{---

----

Sou

rce/

Dra

in E

lect

rode

s---

---}

250 μmSource/DrainW/L = 16

0.4 μm diacrylate

Gate

90 nm pentacene

75 μm PET substrate

Diacrylate monomer

E-beam cure

Pentacene

Abbas et al (2011) J.Vac.Sci.Technol.B, 29, 052401

RR--22--R Vacuum Deposition ProcessR Vacuum Deposition Process

250 μmSource/DrainW/L = 16

0.4 μm diacrylate

Gate

90 nm pentacene

75 μm PET substrate

Diacrylate monomer

E-beam cure

Pentacene

Abbas et al (2011) J.Vac.Sci.Technol.B, 29, 052401

μ=0.09 cm2/VsVT = 10VOn/Off ratio ~ 103

RR--22--R Vacuum Deposition ProcessR Vacuum Deposition Process

Pentacene TFTs on PENPentacene TFTs on PEN

-5.E-06

-4.E-06

-3.E-06

-2.E-06

-1.E-06

0.E+00

1.E-06

-50 -40 -30 -20 -10 0 10

VD (V)

I D (A

)

Vg=-10VVg=-20VVg=-30VVg=-40VVg=-50V

-12

-11

-10

-9

-8

-7

-6

-5

-50 -40 -30 -20 -10 0 10 20

VG (V)

Log 1

0(ID/A

)

I (Vd=-10V)I (Vd=-20V)I (Vd=-30V)

Good saturation, no hysteresis, on/off ratio ~105

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

-50 -40 -30 -20 -10 0 10 20VG (V)

ID0.

5 (A)0.

5

Vd=-10VVd=-20VVd=-30V

0.00

0.01

0.02

0.03

0.04

0.05

-50 -40 -30 -20 -10 0 10 20

VG (V)

Mob

ility

(cm2 /V

s)

VT = -17V to -21V

Pentacene TFTs on PENPentacene TFTs on PEN

Mobility extracted from

⎟⎠⎞

⎜⎝⎛= i

GC

LW

dVId μ

2

Test StructureTest Structure

DNTT Devices on HMDSDNTT Devices on HMDS--treated Si/SiOtreated Si/SiO22S

S

Dinaphthothieno thiophene

DNTT Devices on HMDSDNTT Devices on HMDS--treated Si/SiOtreated Si/SiO22

Effect of purificationEffect of purification

11052•25 Devices•Average Mobility : 0.47 cm2/Vs•Median Mobility : 0.43 cm2/Vs•Standard Deviation : 0.13 cm2/Vs



S

SDinaphthothieno thiophene

DNTT Devices on PENDNTT Devices on PEN

S

SDinaphthothieno thiophene

•PEN substrate, •aluminium gate, •acrylate dielectric•Gold S/D

•29 Devices•Average Mobility : 0.4 cm2/Vs•Median Mobility : 0.4 cm2/Vs•Standard Deviation : 0.13 cm2/Vs

DNTT Devices on PENDNTT Devices on PENS

S

Dinaphthothieno thiophene

Device Stability

Device Modelling with UTMOST 4Device Modelling with UTMOST 4Parameter Extraction

Universal Organic TFT Model (Level=37)

The UOTFT model:An extension of unified charge control model previously used for a-Si and poly-Si TFTs.

Based on:Operation in accumulation mode in the presence of an exponential density of states and interface trapsUnified expression for gate induced charge in the conductive channelUnified charge-based description of mobility and drain-source currentA universal power mobility law valid in all operation regions

Device Modelling with UTMOST 4Device Modelling with UTMOST 4Parameter Extraction

Unified Charge Description of Mobility

( )864.150

4839.841 2 +−=

xxk

O

Tgs

VVV

u−

=

( )( ) ( )⎥⎥⎦

⎤

⎢⎢⎣

⎡

++++⋅=⋅=− +

+

1

1

0 1ln211ln u

u

Oigseiacc eukeVCVCQ

( ) γ

μμ ⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

−⋅=

ACCi

accACC VC

Q 0

μACC characteristic effective mobility in channelVACC characteristic voltage of the effective mobilityVO characteristic voltage of the trap density of

statesVT zero bias threshold voltageγ power law mobility parameter

VG

VDIDMISFET

+ + + + + + +

Device Modelling with UTMOST 4Device Modelling with UTMOST 4Optimisation Routine

Set: TINS, εINS, εS

Extract: VO, VT, μACC and γ from ID-VG plots at low VD

Extract: RS, ASAT and λ from ID-VG plots at high VD

Extract: MSAT,RD from ID-VD plots

Iterate to obtain best fit using different optimisation procedures

Genetic

Marquand-Levenberg

Simulated Annealing

SimulationsEvaporated pentacene bottom-gate TFT on acrylate dielectric

Key parametersμACC = 1.22 x 10-4 cm2/Vs ; VACC = 1.12 V; γ = 1.80; VT = -2.5 V; VO = 0.5 V; RS = 0; RD = 2.47 MΩ

Oxford 01 Newfit

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

-50 -40 -30 -20 -10 0VG (V)

I D (A

)

Vd= -10V (exp)-20V-30VVd= -10V (sim)-20V-30V

Oxford 01 Newfit

-4.E-06

-3.E-06

-2.E-06

-1.E-06

0.E+00

-50 -40 -30 -20 -10 0

VG (V)

I D (A

) Vg= -10V

-20V

-30V

-40V

-50V

Transfer Characteristics Output Characteristics

SimulationsEvaporated DNTT bottom-gate TFT on acrylate dielectric

-10

-9

-8

-7

-6

-5

-4

-60 -50 -40 -30 -20 -10 0VG (V)

Log 1

0(ID/A

)

MeasuredSimulated

-2.5E-05

-2.0E-05

-1.5E-05

-1.0E-05

-5.0E-06

0.0E+00

-60 -50 -40 -30 -20 -10 0

VD (V)

ID (A

)

Vg=0V-10V-20V-30V-40V-50V-60V

Transfer Characteristics Output Characteristics

Device 08

-6.E-06

-5.E-06

-4.E-06

-3.E-06

-2.E-06

-1.E-06

0.E+00

-60 -50 -40 -30 -20 -10 0

VD (V)

ID (A

) Vg=0V-10V-20V-30V-40V-50V-60V

Key parametersμACC = 1.02 x 10-3 cm2/Vs ; VACC = 1.00 V; γ = 0.93; VT = -4.48 V; VO = 0.013 V; RS = 0; RD = 0 Ω

SimulationsSpin-coated top-gate TFT with Teflon dielectric

Output CharacteristicsDevice 08

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

-60 -50 -40 -30 -20 -10 0

VG (V)

ID (A

)

Vd=-60V (expt)Vd= -60V (sim)

Transfer Characteristics

Inverter ResponseSpin-coated top-gate TFT with Teflon dielectric

-VDD

0

-VDD0

-VDDT 08

T 07T 08

T 07

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

-60 -50 -40 -30 -20 -10 0 10

VG (V)

I D (A

)

Device07

Device08 (norm)

Scalability of Device CharacteristicSpin-coated top gate TFT with Teflon dielectric

Device07 Device08

W (μm) 15900 1800

Gateway Simulation of Inverter ResponseGateway Simulation of Inverter ResponseSpincoated OSC

-40

-35

-30

-25

-20

-15

-10

-5

0

-40 -30 -20 -10 0 10 20

Vin (V)

Vout

(V)

Vdd=-10V-20V-30V-40V

Inverter based on DNTT TFT on PENInverter based on DNTT TFT on PEN

-VDD

0

-VDD0

-VDDT 09

T 10

-60

-50

-40

-30

-20

-10

0

-40 -30 -20 -10 0 10

Vin (V)

Vou

t (V)

-4

-3

-2

-1

0

Gai

nVdd = -20V -40V-60V

Inverter based on DNTT TFT on PENInverter based on DNTT TFT on PENScalability check

EP Device 9

-10

-9

-8

-7

-6

-5

-60 -50 -40 -30 -20 -10 0

VG (V)

Log 1

0(I D

/A)

Device 9Device 10 (norm)

Inverter based on DNTT TFT on PENInverter based on DNTT TFT on PENSimulation (lines) Simulation (lines) vsvs ExperimentalExperimental (points)

-60

-50

-40

-30

-20

-10

0

-50 -40 -30 -20 -10 0 10Vin (V)

V out

(V)

Vdd=-20V-40V-60V

ConclusionsConclusions

Excellent progress in the vacuum-preparation of gate dielectric

Mobility in all vacuum prepared DNTT TFTs ~ 0.4 cm2/Vs

High on/off ratio 103 – 105

Early attempts at circuit simulation encouraging

Very good inverter action using DNTT TFTs

Device fabrication now needs to be optimised

Improvements required in parameter extraction and circuit simulation

Acknowledgements Acknowledgements

Academic TeamAcademic Team

BangorEifion PatchettAled WilliamsColin Watson

OxfordHazel AssenderGamal AbbasZiqian Ding

ManchesterSteve YeatesJohn Morrison

Funders and Industrial AdvisersFunders and Industrial Advisers

http://www.epsrc.ac.uk/default.htm

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