Device engineering for β-Ga O -based high power electronics

Saurabh Lodha*, Siddharth Rajan†,‡, Chandan Joishi*,†, Zhanbo Xia†,

Joe McGlone†, Yuewei Zhang†, Aaron. R. Arehart†, Hongping Zhao†,‡,

Dipankar Biswas*, Steven Ringel†,‡

*Dept. of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India

†Electrical and Computer Engineering,‡Materials Science and Engineering,

The Ohio State University, Columbus, OH, USA

Funding: IMR-OSU IITB Alliance, DTRA, AFOSR GAME MURI, DST (GoI), MeitY (GoI)

Device engineering for β-Ga2O3-based high power electronics

[email protected]

Outline

2/25

§ β-Ga2O3: Background and motivation

§ Device fabrication/characterization

§ Modulation doped FETs

§ Delta doped MESFETs

§ Enhancement-mode MOS Capacitors

§ Conclusions

mailto:[email protected]

[email protected]

Power devices: application space

GaN power device industry

Yole development 2019

Technology opportunities:o power switching applications o mm-wave power

Ga2O3

Ga2O3

3/25

𝛽-Ga2O3

SiC


[email protected]

β-Ga2O3: Introduction

β- phase: Monoclinic crystal structureOther polymorphs : α, γ, δ and ε

§ Melt-based growth techniques§ First wide-band gap material

§ High quality low cost native substrates

§ Homo-epitaxy§ Low defect density

§ Controlled n-type doping (Si, Sn, Ge)/ insulating (Fe, Mg) films

§ ρ = 10-3 – 1012 Ω.cm, n = 1014 – 1020 cm-3

§ p-type Ga2O3Band gap = 4.6 eV

4/25


[email protected]

Power switching parameters§ RON (on-state resistance)

§ Conduction loss§ Dominance at low frequencies

§ Qg (gate-charge)§ Charges to drive the ON-OFF transition

§ Switching loss§ VBR (Breakdown voltage)

§ Max voltage the device can block in off-state

ON OFFOFF

Pow

er

time

Cathode

Anode

Drift layer

(low doped n-type)

Substrate

Wdep

0

x

𝑅!" =𝑊#$%

𝑞𝜇"𝑁&=

4𝑉'()

𝜺𝒔𝝁𝒏𝑬𝑪𝟑Baliga’s FoM

𝑅!"𝑄. =4𝑉'()

𝝁𝒏𝑬𝑪𝟐Baliga’s high frequency FoM

Properties Si GaAs 4H-SiC GaN Ga2O3

Baliga’s FoM (εµEC3) 1 16 250 870 2916

Baliga’s high freq. FoM (µEC2) 1 11 46 100.8 118.5

FoM’s calculated for EC = 8 MV/cm, µn = 250 cm2/Vs

𝑃!"## ~ 𝐼"$%& 𝑅𝑂𝑁 + 𝐼"$%𝑉'()!*!𝑓#+

5/25


[email protected]

Critical electric field§ Device metrics

§ Low RON for a given VBR

§ Predicted EC = 8 MV/cm§ p-n band-to-band tunneling

§ Real picture§ EC ~ 3-4 MV/cm: Schottky leakage

§ Breakdown field calculation (unipolar device)§ Avalanche breakdown

§ Upper limit on device performance

6/25

102 103 10410-1

101

103

RO

N (m

W.c

m2 )

VBR (V)

Si

4H-SiC GaN β-Ga2O3

Cathode

Anode

Drift layer

(Low doped n-type)

Substrate

Wdep

0

x

Credit: Zhanbo Xia

EGEc

EF

Ev

p-n

800 1000 1200-4

-2

0

2

4

Ener

gy (e

V)

Length (nm)


[email protected]

Importance of carrier mobility

§ AlGaN/GaN HEMTs § Lateral power devices

§ Ga2O3 heterojunction capability § Design of (AlGa)2O3/Ga2O3 FETs.§ Lateral power devices

§ Degradation in RON => dynamic RON

§ Peak field at gate edge § Field-plate (FP): additional electrode for E lines termination§ Power switching: Enhancement-mode operation

7/25

S G D

Cap

SubstrateBuffer

2-DEG

Surface states

Expected

Data

S D

UID β-Ga2O3 buffer

Fe- doped (010) β-Ga2O3 substrate

Si d- dopingUID β-Ga2O3 cap

Gn+

β-Ga2O3

S D

UID β-Ga2O3 buffer



FP

G Passivationn+

β-Ga2O3

S G D

-VGS +VDSPassivation

(b) (c) (d)Substrate

+ + + + + + + +

S G D

-VGS +VDS

(a)

Channel

Cap

SubstrateBuffer

+ + + + + + + +E lines E lines

RON


[email protected]

Outline

8/25





§ Charge trap layer: e-mode devices

§ High-k/bilayer dielectric field management

§ Conclusions


[email protected]

MBE growth of β- Ga2O3 (OSU)

• Substrate: Bulk (010) β- Ga2O3

• Substrate Temperature: 700o C

• O2 plasma power : 300 W

• Ga flux: 8x10-8 Torr (O-rich conditions)

• Chamber pressure: 1.5x10-5 Torr

• Growth Rate: 240 nm/ hour

Okumura et. al. (Speck Group- UCSB)

• Vertical MBE system (Riber M7) – O Plasma PAMBE

• Sources:

• O plasma (unibulb), Ga, Si, Al, Fe

9/25


[email protected]

(AlGa)2O3/ Ga2O3 MODFETs

0 20 40 60 800

1x1019

2x1019-6-4-202

n s (cm

-3)

Depth (nm)

EV

Ener

gy (e

V)

EC

EF

Dopants

Channel


UID β-Ga2O3 (buffer)

Si δ-doping

2-DEG

(AlXGa1-X)2O3 barrier

(AlXGa1-X)2O3 spacer

• Dopants spatially separated from channel

• Eliminate ionized impurity scattering

• Enhanced mobility

• Thickness confirmed from STEM

• Al composition (22%) from HRXRD

60 61 62 63 64100

103

106

Cou

nt (a

.u.)

2q (degree)

β-Ga2O3 (020)

β-(Al0.22Ga0.78)2O3

1 μm 0 nm

10 nm

Sriram et al., APL 2017, Joishi et al., IEEE EDL, 2019

10/25


[email protected]

(AlGa)2O3/ Ga2O3 MODFET: Field plate engineering

1 µm

LFP = 550 nmGate

Field-platePt

SiNx

• To engineer peak field at the gate-drain edge

• SiNx as the passivation dielectric (140 nm)

• Hall mobility

• Room T: 101 cm2/Vs @ 3.4X1012 cm-2

• Device parameters (LSD = 2 µm)

• ID, max = 42 mA/mm

• VP = -1.2 V

• ION/IOFF = 107

11/25

0 2 4 6 8 100

10

20

30

40

50

I DS (m

A/m

m)

VDS (V)

VGS=2 V, ΔVGS= -500 mV

-2 -1 0 1 210-6

10-4

10-2

100

102

VGS (V)

I DS (m

A/m

m)

0

5

10

15

g m (m

S/m

m)VDS = 10 VLFP

SiNx

S G

Fe- doped (010) β-Ga2O3substrate

n+

Ga2O3

DSi δ-doping

2-DEG

Joishi et al., IEEE EDL, 2019


[email protected]

(AlGa)2O3/ Ga2O3 MODFET: device characteristics

§ Pulsed IV§ SiNx passivation: improved knee-walkout

Breakdown measurements • Device in off-state• For LGD = 250 nm, FAVG = 3.9 MV/cm• For LGD = 16 µm, VBR = 1370 V• Schottky gate limited breakdownRON-VBR benchmarking• Data far-off from intrinsic limit.

12/25

0 2 4 6 8 100

10

20

30VGS = 2 V, DVGS = - 500 mV

I DS

(mA/

mm

)

VDS (V)

Line : DC Symbols : 5 µs

0 2 4 6 8 100

10

20

30

40

I DS

(mA/

mm

)

VDS (V)


VGS = 2 V, DVGS = - 500 mV

0 2 4 6 8 100

10

20

30VGS = 2 V, DVGS = - 500 mV

I DS

(mA/

mm

)

VDS (V)


0 2 4 6 8 100

10

20

30

40

I DS

(mA/

mm

)VDS (V)


VGS = 2 V, DVGS = - 500 mV

102 10310-1

101

103

RO

N (m

W.c

m2 )

VBR (V)

From literature This work

ECS ’19

EDL ’17

EDL ’17APL ’12

EDL ’16

DRC ’13

EDL ’19

EDL ’16

EDL ’17EDL ’18


[email protected]

Increasing channel charge density

§ Designs to increase charge density

§ Modulation doped FETs§ Increase the conduction band offset

§ Increasing the Al percentage

§ Bottleneck: epilayer growth

§ Quantum well MODFETs§ Multiple channels:

§ Secluded 2-DEG: growth challenge ?


Multiple channel MODFETs

Delta doped MESFETs

13/25

S G


25 nm AlGaO barrier

5 nm AlGaO spacer

n+

Ga2O3

100 nm UID β-Ga2O3 (buffer)

D

Si δ-doping

2-DEG

GS


5 nm AlGaO barrier

5 nm AlGaO spacer

250 nm UID β-Ga2O3 (buffer)

D

25 nm AlGaO barrier

5 nm AlGaO spacerSi δ-

doping

n+

Ga2O3 3 nm Ga2O3 QW

S G

UID β-Ga2O3 (cap)


D

Si δ-doping

n+

Ga2O3


0 30 60 90

0.0

0.5

1.0

1.5

2.0

Ener

gy (e

V)

Depth (nm)

Ec

EF


[email protected]

Outline

14/25





§ Charge trap layer: e-mode MOS Capacitors


§ Conclusions


[email protected]

β- Ga2O3 delta doped MESFET

0 10 20 30 40 50

-4

-2

0

2El

ectro

n C

once

ntra

tion

(cm

-2)

EF

EC

Ener

gy (e

V)

Depth (nm)

Ev

0

1x1019

2x1019

3x1019

• High concentration of 2-DEG

• Enables scaling of gate-channel distance

• High gate breakdown voltage

• For similar doping density

• Higher mobility than uniformly doped films

• Flat C-V characteristics

• 2-DEG profile: (1.2x1013 cm-2 charge density)

S G

UID β-Ga2O3 (cap)


D

Si δ-dopingn+

Ga2O3


35 nm

100 nm

15/25

0 10 20 30 40 50 600

1x1019

2x1019

3x1019

Ele

ctro

n C

once

ntra

tion

(cm

-3)

Position (nm)

NS =1.2 x1013 cm-2

-10 -8 -6 -4 -2 0

0.0

0.1

0.2

0.3

C G (

F/cm

2 )

VGS (V)

f = 1 MHz

Zhanbo et al., EDL 2018


[email protected]

β- Ga2O3 delta doped MESFET

16/25

• Breakdown characteristics

• VBR = 175 V, LGD = 1.3 um, FAVG = 1.3 MV/cm

• RON better than single channel MODFETs

• Field management design

• Dispersion characteristics

• Significant knee-walkout

• Source

0 5 10 150.0

0.1

0.2

I DS

(A/m

m)

VDS (V)


VGS = 2V, DVGS = -2V

S G

UID β-Ga2O3 (cap)


D

Si δ-doping

n+

Ga2O3


102 10310-1

101

103

RO

N (m

W.c

m2 )

VBR (V)


ECS ’19

EDL ’17

EDL ’17APL ’12

EDL ’16

DRC ’13

EDL ’19

EDL ’16

EDL ’17EDL ’18

102 10310-1

101

103

RO

N (m

W.c

m2 )

VBR (V)


ECS ’19

EDL ’17

EDL ’17APL ’12

EDL ’16

DRC ’13

EDL ’19

EDL ’16

EDL ’17EDL ’18

MODFET

δ-FET


[email protected]

Source of dispersion: Fe doped substrate

17/25

S GUID β-Ga2O3 (cap)


D

Si δ-dopingn+

Ga2O3


Buffer thickness

100 nm 300 nm 600 nm

Lines: DC, Symbols: Pulsed

0 5 10 150.0

0.1

0.2VGS = 2 V, DVGS = -2 V

I DS

(A/m

m)

VDS (V)0 5 10 15

0.0

0.1

0.2VGS = 2V, DVGS = -2V

I DS

(A/m

m)

VDS (V)0 5 10 15

0.0

0.1

0.2

I DS

(A/m

m)

VDS (V)

VGS = 2V, DVGS = -2V

§ Dispersion characteristics§ Thicker buffer FET

§ Reduced dispersion

§ Lower RON degradation

§ Fe a source of dispersion


[email protected]

Epitaxial passivation: β-Ga2O3 delta doped MESFET

S D

450 nm UID β-Ga2O3 buffer

Fe- doped (010) β-Ga2O3

substrate

Si d- doping40 nm UID β-Ga2O3 cap

FP

G 120 nm

Epitaxial UID β-Ga2O3 passivation

n+

β-Ga2O3

Ex situ passivation§ Non-ideal dielectric/β-Ga2O3 interfaceEpitaxial passivation§ Semiconductor-dielectric interface absent

§ No interface exposure to high fields§ Ex situ surface far off from the 2-DEG§ Better dispersion properties

§ High dielectric constant of β-Ga2O3

§ Better breakdown characteristics

18/25

S G

UID β-Ga2O3 (cap)


D

Si δ-dopingn+

Ga2O3

Fe- doped (010) β-Ga2O3

substrate

Dielectric

Source

Drain

LSD = 5.4 µmRecessLGS = 2 µm

LFP = 0.4 µmLG = 0.65 µm

LGD = 2.7 µm

Gate

FP


[email protected]

Transistor characteristics

Pulsed IV§ Better dispersion characteristics

Breakdown characteristics§ VBR = 315 V, FAVG = 2.3 MV/cm

§ RON vs VBR benchmarking

19/25

0 5 10 150.00

0.05

0.10

0.15

0.20I D

S (A

/mm

)

VDS (V)

VGS = 1 V, DVGS = -2 V

0 100 200 3000.000

0.005

0.010

0.015 Black: ID Red: IG

Cur

rent

(mA/

mm

)

VDS (V)

No FP

with FP

LGD = 1.4 µm

Further device engineering needed!Joishi et al., IEEE TED 2020

102 10310-1

101

103R

ON (m

W.c

m2 )

VBR (V)


ECS ’19

EDL ’17

EDL ’17APL ’12

EDL ’16

DRC ’13

EDL ’19

EDL ’16

EDL ’17EDL ’18

102 10310-1

101

103

RO

N (m

W.c

m2 )

VBR (V)


ECS ’19

EDL ’17

EDL ’17APL ’12

EDL ’16

DRC ’13

EDL ’19

EDL ’16

EDL ’17EDL ’18

102 103 10410-1

101

103

RO

N,S

P (m

B.c

m2 )

VBR (V)

Lateral FETs Vertical FETs

β-Ga 2O

3

GaN

4H-SiC

Our work

118 MW/cm

2

Si

101 102 103 10410-1

101

103

From literature MODFET d-MESFET

RO

N (m

W.c

m2 )

VBR (V)

102 10310-1

101

103

RO

N (m

W.c

m2 )

VBR (V)


ECS ’19

EDL ’17

EDL ’17APL ’12

EDL ’16

DRC ’13

EDL ’19

EDL ’16

EDL ’17EDL ’18

Our previous work


[email protected]

Device engineering: towards enhancement mode transistors

• Channel charge density > 1.5x1013 cm-2: Significant gate leakage

• Need for dielectrics

• Conventional dielectric for β-Ga2O3: Al2O3

• High dielectric constant

• Positive fixed oxide charge (NOX)

• D-mode operation

• High channel charge density pinch-off

• SiO2 as a dielectric on Ga2O3

• Highest known ΔEc till date

• Reduced gate leakage

• Negative NOX

• E-mode operation

• Bilayer dielectric (Al2O3/SiO2)

• Leverage the combined benefits of SiO2 and Al2O3

Al2O3 β-Ga2O3

20/25

S D

UID β-Ga2O3 buffer


2-DEG channel

Barrier layer

Gn+

β-Ga2O3

High-K passivationDielectric

FP

Al2O3 SiO2 β-Ga2O3

@VGS = 0 V


[email protected]

Outline

21/25





§ Enhancement-mode MOS Capacitors


§ Conclusions


[email protected]

ALD growth of dielectrics (IITB)

SiO2

• Tris(dimethylamino)silane• O2 plasma: 300 W• Temperature: 250 oC

Al2O3

• Trimethyl aluminum (TMA)• Thermal (DI water)• Temperature: 250 oC

AlN• Trimethyl aluminum (TMA)• NH3 plasma: 300 W• Temperature: 200 oC

• Cambridge Nanotech Fiji 200 ALD system• Plasma sources: O2, N2, NH3

• Depositions (Plasma/Thermal)• SiO2, Al2O3, HfO2, ZrO2, AlN, TiN, TiO2, Nb2O5

22/25


[email protected]

Device characteristics

Al2O3 Al2O3/SiO2

• Total charge depleted• ~1.6x1013 cm-2

• Steep depletion characteristics• Better interface, low DIT

• Negative NOX: normally-OFF operation• Poor VFB retention

VFB retention

23/25

Dipankar et al., APL 2019


[email protected]

Charge trap layer

Al2O3/SiO2

Ti/AuNi/Au

• To engineer negative NOX for e-mode operation

• Addition of a charge trap (C.T) layer

• Non-polarized AlN as a CT layer

• VFB domain

• [3.5 V, 10 V]

• Charge depleted

• 1.5x1013 cm-2

• Excellent charge retention

• @ RT and 55 oC

Ti/AuNi/Au

CT layer

Tunnel dielectric

Blocking dielectric

CT layer (AlN)

Al2O3 SiO2 β-Ga2O3

24/25Dipankar et al., APL 2020


[email protected]

Conclusions§ Ga2O3 for power electronics

§ Melt-based growth: cost factor?

§ FoM’s for Ga2O3: shows promise but are simple guides§ ON-resistance vs field management in MODFETs and δ-FETs§ AlN as a charge trap layer for tunable VT transistors

The future

§ Delta-doped FETs from OSU + AlN charge trap layer at IITB§ Enhancement mode delta-doped FETs

§ Development of high-K dielectric BZN at IITB

§ Field management designs at OSU and IITB

25/25

Ti/AuNi/Au

CT layer

Tunnel dielectric

Blocking dielectricS D

UID β-Ga2O3 buffer


2-DEG channel

Barrier layer

Gn+

β-Ga2O3

S D

UID β-Ga2O3 buffer


2-DEG channel

Barrier layer

FPG

High-K passivation

n+

β-Ga2O3

Dielectric

(OSU) (IITB)


[email protected]

Thank you


[email protected]

Backup slides


[email protected]

Importance of carrier mobility

§ AlGaN/GaN HEMTs § Lateral power devices

§ Ga2O3 heterojunction capability § Design Ga2O3 FETs that enable

§ High mobility x charge density.

§ Lateral power devices§ Degradation in RON => dynamic RON

RONID, MAX

7/25

S G D

Cap

Substrate

Buffer

2-DEG

-VGS +VDS

E lines++++++++++++

Ionized states


[email protected]

S D

UID β-Ga2O3 buffer



Gn+

β-Ga2O3

S D

UID β-Ga2O3 buffer



FP

G Passivationn+

β-Ga2O3

S G D



+ + + + + + + +

S G D

-VGS +VDS

(a)

Channel

Cap

SubstrateBuffer


Passivation

VGS = -5 VLGD = 1.3 um

Compliance = 1nA

VGS = -5 V

LGD = 16 um

(b)

0 5 10 150

500

1000

1500

VBR

FAVG, BR

LGD (µm)

V BR (V

)

1

2

3

4 E

lect

ric fi

eld

(MV/

cm)

(a)

(d)(c)

0 2 4 6 8 100.1

0.0

-0.1

-0.2Ve

rtica

l dim

ensi

on (µ

m)

Lateral dimension (µm)

FP

DG

n+

Ga2O3

2 30

2

4

6

8

with FP w/o FP

Elec

tric

field

(MV/

cm)

Distance (µm)

VGS = -5 VLGD = 1.3 um

Compliance = 1nA

VGS = -5 V

LGD = 16 um

(b)

0 5 10 150

500

1000

1500

VBR

FAVG, BR

LGD (µm)

V BR (V

)

1

2

3

4

Ele

ctric

fiel

d (M

V/cm

)

(a)

(d)(c)

0 2 4 6 8 100.1

0.0

-0.1

-0.2

Verti

cal d

imen

sion

(µm

)Lateral dimension (µm)

FP

DG

n+

Ga2O3

2 30

2

4

6

8

Elec

tric

field

(MV/

cm)

Distance (µm)

Motivation: breakdown field management

G D

BA BA

BA BA

§ Field-plate (FP): additional electrode for E lines termination§ Power switching: Surface passivation, field-plate, e-mode operation

8/25

S D

UID β-Ga2O3 buffer



Gn+

β-Ga2O3

S D

UID β-Ga2O3 buffer



FP

G Passivationn+

β-Ga2O3

S G D



+ + + + + + + +

S G D

-VGS +VDS

(a)

Channel

Cap

SubstrateBuffer



[email protected]

Field engineering: High-K dielectrics

Ref: Zhanbo et al., APL 2019

27/25

S D

UID β-Ga2O3 buffer


2-DEG channelBarrier layer

FPG

High-K passivation

n+

β-Ga2O3

Dielectric

• High-K dielectric to reduce peak field at the gate edge.

• MIS diodes using Nb2O5 (dielectric constant = 50)

Credit: Prabhans, Jayeeta


[email protected]

Vertical topology: field management using bilayer dielectrics

[100] Ga2O3

• Leveraging the combined benefits of a high-K/ low-K dielectric combination

28/25Credit: Ravikiran


Device engineering for β-Ga O -based high power electronics

Documents

Transcript of Device engineering for β-Ga O -based high power electronics