© 2009 Solido Design Automation

WHITE PAPER

Rapid and Accurate

Verification & Design of High-σ Circuits with

Variation Designer: Verify High-Sigma Design

Verify High-Sigma Design

© 2009 Solido Design Automation

Introduction In today’s highly competitive semiconductor industry, profitability hinges on high yield, competitive design performance, and rapid time to market. For the designer, this translates to the need to manage diverse variations (global and local process variations, environmental variations, etc.), reconcile yield with performance (power, speed, area, etc.), while under intense time pressures. This is an enormous challenge; and it is getting even harder due to more process variations at each new technology node.

Some circuit blocks, such as memory bitcells, are repeated thousands, millions, or even billions of times on a die. For the overall chip to have good yield, the repeated block must have extremely high yield (low probability-of-failure pf). Let us consider a chip with target yield of 99.0% (pf ≤0.01), having 1 million bitcells. To achieve the target chip yield, each bitcell needs yield ≥ 99.999999% (pf ≤1.0e-8)1

Let us consider how one might compute the yield of such a circuit.

.

1. Plain MC: One approach would be to use Monte Carlo sampling. However, this would require far too many simulations: a circuit with 99.9999% yield would need, on average, 1 million samples from the true distribution just to observe a single failure against circuit specifications. This is clearly not feasible.

2. MC + Gaussian: Another approach is to do a moderate number of simulations (say 100 or 1000), compute the mean and standard deviation, “pretend” the distribution of performance is Gaussian, and compute yield as the area under the Gaussian where specifications are met. The issue is that distributions of circuit performances are often not Gaussian in practice. A Gaussian distribution only arises when there is a linear mapping from process variables to performance2

3. Manual Model: A third approach is to manually construct analytical models relating process variation to performance and yield. However, this is highly time-consuming to construct, is only valid for the specific circuit and process, and may have accuracy issues. A change to the circuit or process renders the model obsolete.

. For circuits, the mapping can be highly nonlinear.

None of the previous approaches are adequate. Clearly, there is a need to quickly and

Furthermore, in the case when yield needs to be improved, there is no means to do rapid iterations on high-yield circuit designs.

accurately estimate yield for high-yield circuits.

1 For simplicity of description, this assumes that we have just local (not global) process variations, and there is no redundancy, error correction, etc. 2 Another condition is that the distribution of process variations must be Gaussian, but this is often a sufficiently accurate approximation [1]

Verify High-Sigma Design

© 2009 Solido Design Automation

Overview Solido Verify High-Sigma Design was created to address the demands of statistical verification and design in modern high-yield circuits.

Its key features are:

• Determines an accurate yield estimate

• Enables rapid design iterations, via

for high-yield circuits, using a low number of circuit simulations. It uses SPICE in the loop, for accuracy and portability.

design-specific high-σ corners

.

Value Compared to a plain Monte Carlo simulation, Verify High-Sigma Design (VHS) is orders of magnitude faster for estimating yields of high-σ circuits. Compared to MC + Gaussian or a Manual Model approach, VHS is far more accurate, as it does not make any simplifying assumptions.

Additional value arises when the user extracts design-specific corners from a VHS run. These corners highlight the circuit failure cases that must be fixed. By designing against just these corners, the designer can perform rapid design iterations to improve the design.

What is “Sigma”? Yield values are often specified in terms of sigma (σ). Sigma can be computed from yield, and vice versa. Yield is the area under a Gaussian density function in the range -σ to +σ. Effectively, sigma is defined by that conversion. Typical values are:

Sigma (σ) Yield 1 68.27% 2 95.44% 3 99.730% 4 99.9936% 5 99.999943% 6 99.99999980%

Verify High-Sigma Design

© 2009 Solido Design Automation

Technology With a normal Monte Carlo run, process points are drawn directly from the process variation distribution. The problem, as noted earlier, is that far too many samples are needed in order to get failures in the design. Verify High-Sigma Design changes this by sampling from a different distribution, in which a greater proportion of samples are failures. This approach is a variant of importance sampling [2][3]. Verify High-Sigma Design estimates the yield of high-sigma circuits by: 1. Creating a new sampling distribution such that a greater proportion of samples are failures. 2. Drawing samples from the new distribution, simulating them, and seeing if they meet

specifications . 3. Estimating yield by mathematically unbiasing the samples, according to importance

sampling formulae [2]. 4. Computing yield accuracy, using a statistical technique called bootstrapping [4]. To illustrate that Verify High-Sigma Design (VHS) returns yield estimates as accurate as a standard Monte Carlo (MC) run, the following table compares MC and VHS yield estimation results across 6 different circuits on moderate-yield circuits (moderate yield so that MC only needs a moderate number of samples to make a good yield estimate). We see that, for all 6 cases, the yield estimates for VHS and MC agree because their yield confidence bounds overlap.

Circuit MC Yield (up to 10K samples) VHS Yield (250 samples) Current mirror 99.580% (99.433% - 99.689%) 99.709% (99.569% - 99.808%) GMC 99.836% (99.519% - 99.944%) 99.831% (99.752% - 99.885%) LNA 99.950% (99.883% - 99.979%) 99.888% (99.760% - 99.9662%) Folded opamp 99.221% (98.027% - 99.699%) 99.490% (98.639% - 99.370%) CP 99.597% (99.410% - 99.725%) 99.522% (99.291% - 99.682%)

Target Applications Verify High-Sigma Design (VHS) is applicable for estimating yield and extracting corners for any circuits which have high or even medium sigma values (say, >4 sigma).

These include:

• Memory circuits: bitcells, sense amps, full rows or columns at once

• Highly replicated digital circuits

• Any other type of circuit with high or medium sigma. This is possible because VHS is independent of the semiconductor process, or circuit type, and uses SPICE for feedback.

The following plots illustrate the behavior of VHS on two circuits: a sense amp (left) and a voltage reference (right). Note how the yield estimate converges over time.

Verify High-Sigma Design

© 2009 Solido Design Automation

These plots have results that are remarkable than first glance. For example with the sense amp, see that probability of failure is about 1 in 108.2. This means that normal MC sampling would have taken about 100 billion samples to get a single failure. In contrast, VHS had a good estimate after 4000 samples.

A Complete Variation-Aware Solution Verify High Sigma Design (VHS) is an integral part of Solido’s Variation Designer platform and toolset. Variation Designer enables designers to eliminate design loss due to uncontrollable variations and time-to-market constraints: rather than inadvertent over-design or under-design, right design is achievable.

Once the user has high-sigma corners from VHS, he or she may design against those corners using other Variation Designer applications, such as Run Corners and Sweep Design Variables. Once VHS has been used to validate the design (against statistical and environmental variations), the designer may use Solve Proximity to manage proximity variations.

Verify High-Sigma Design

© 2009 Solido Design Automation

Use Model: Verification Getting started with Verify High Sigma Design is straightforward – as simple as performing a plain Monte Carlo run.

From the main Variation Designer application, there is simply a tab for Verify High Sigma Design, which the user selects. The setup choices are straightforward: circuit specifications, and number of samples. Circuit specifications come from the designer’s requirements. Number of samples guides how accurate the user would like the yield estimate: a lower number of samples means a wider confidence interval in the yield estimate. Note that the VHS engine will keep running until it can at make at least one good yield estimate, even if that means exceeding the user-specified number of samples.

Once the application is running, VHS updates all simulation results in real time on the plots and tables. In the scatterplots, note that these are not the true distribution of the process variations, but rather an altered version which is biased towards having more infeasible samples.

When the VHS engine has sufficient information to make a yield estimate, it will return that yield estimate. If it still has more simulations left, it will take them and will continually update the yield estimate with tighter confidence intervals. The engine will stop once it makes a yield estimate and has exhausted the maximum number of simulations.

Use Model: Corner Extraction This use model picks up where Verification ends off, in the case when the yield is not acceptable. Therefore, the circuit must be improved.

It would be time-consuming and tedious to make changes to the circuit, then do a full VHS verification, and iterate until the circuit is acceptable. A faster (yet accurate) method is to find representative failure cases to design against, i.e. design-specific corners. The results of a VHS run can, in fact, be exploited to extract such corners.

The flow is: when the yield is not acceptable, the user examines the 2d scatterplots and selects process point(s) that cause infeasibility. These can be the points near the feasibility boundary (the most likely points); or ones a little deeper into the infeasibility region (which, if solved against, will give higher margin). The user adds these to Variation Designer’s set of corners.

Then, the designer uses the Variation Designer applications for corner-based design: Run Corners, Sweep Design Variables, etc. Once he is satisfied with the design’s performance against corners, the designer invokes a new VHS to verify the circuit. If needed, the designer performs more design iterations with additional corners.

Verify High-Sigma Design

© 2009 Solido Design Automation

Return On Investment When design teams and managers consider which advanced technologies to incorporate in their flows, their metrics include quality of results (QoR), use model, ease of adoption, and cost.

Verify High Sigma Design technology addresses each of these metrics. Designers can improve the quality of their results by changing their designs using High-Sigma extracted corners. They can statistically verify their designs with SPICE accuracy in a short amount of time; these two qualities were not previously achievable. Once a user is on the easy-to-use Variation Designer platform, adopting and using Verify High-Sigma Design is straightforward.

Summary Semiconductor profitability hinges on high yield, competitive design performance, and rapid time to market. For the designer, this translates to the need to manage diverse variations (global and local process variations, environmental variations, etc.), reconcile yield with performance (power, speed, area, etc.), while under intense time pressures.

With high-σ designs, where failures are one in a million, previous approaches to verifying those designs were either extremely expensive or inaccurate.

Verify High-Sigma Design allows the designer to quickly and accurately verify high-σ designs. Furthermore, it enables rapid design iterations, via design-specific high-σ corners.

References: [1] P. G. Drennan, C. C. McAndrew, “Understanding MOSFET Mismatch for Analog Design,” IEEE J. Solid State Circuits, March 2003. [2] T.C. Hesterberg, Advances in importance sampling. Ph.D. Dissertation, Statistics Department, Stanford University, 1988. [3] D.E. Hocevar, M.R. Lightner, and T.N. Trick, "A Study of Variance Reduction Techniques for Estimating Circuit Yields", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 2, No. 3, July 1983, pp. 180-192. [4] B. Efron, “Bootstrap Methods: Another Look at the Jackknife”, The Annals of Statistics , Vol. 7, No. 1, 1979, pp. 1-26.

Verify High-Sigma Design

© 2009 Solido Design Automation

Solido Design Automation, Inc. http://www.solidodesign.com USA & Canada Sales 111 North Market Street, Suite 300 San Jose, CA 95113 +1 408 332 5811 na.sales@solidodesign.com Japan Sales 090 3910 4163 Email: japan.sales@solidodesign.com Asia-Pacific Sales +1 408 332 5811 x 5728 asia.sales@solidodesign.com Europe Sales Sipeda +44 (0) 1386 550101 europe.sales@solidodesign.com