Post on 16-Mar-2018
1.0 CMOS OPAMP
1.1. General Opamp Block Diagram
A1 -A2 A3
Cc
V1 V2VOVin
Differentialstage gain
Inverterstage gain
Bufferstage gain
Figure 1. Opamp General Block Diagram Note the second stage needs to have a negative gain because of the feedback capacitor. With a positive gain an oscillator or unstable system will be implemented instead. The last stage is a buffer to convert the high output impedance of the inverter stage to a low output impedance. This is needed in developing a good opamp. Ideal opamp requires rin =∞ and ro=0. Figure 2. The Effect of Compensation Capacitance Cc. At the input side,
A)1(sC1
IV ;
sC1
IA)1(V ;
sC1
IAVV ;
sC1
IVV
c1
1
c1
1
c1
11
c1
21
+==
+=
+=
−
This is known as the miller capacitance. The feedback capacitance value appears at the input side of the gain stage with a value magnified by (1+A). At the output side,
1>>A when ;sC
1
)A11(sC
1IV ;
sC1
I
)A11(V
; sC
1I
AVV
;sC
1I
VV
cc
2
2
c2
2
c2
22
c2
12 =+
==+
=+
=−
1
Due to Miller effect, the load of the first stage is effectively the compensation capacitance Cc magnified by (1+A2)
A1Vin V1
Cc(1+A2)=Ceq =A2Cc
Figure 3. The Miller Capacitance Loading the First Stage. The gain
o1m2o1m1in
1 ZgZgVV=A1 =−=
where:
Z rds2 / /rds4 / /1
sC1
sC s(1+ A2)C sA2Co1eq eq C C
≅
≅ = ≅
1 1
The voltage gain of the opamp, assuming the output buffer has unity gain (A3=1),
sCcg
sCcgA3
sA2CcgA3A2=A3A2A1
VV
=Av(s) m2m2m2
in
o ==
=
The unity gain bandwidth, wGB is the radian frequency when the gain is 1. That is,
1Ccjw
g)Av(jwAv(s)
GB
m2GB ===
Solving for wGB,
C
m2GB C
gw =
1.2. Slew Rate Determination
2
VDD
M5
M1 M2
M3 M4
-A2
CcVin- Vin+
V1 V2
Vbias
Differential stage gain
Inverter stage gain
Figure 4. The Differential Gain Stage of the Opamp. Slew rate is the maximum rate at which the output changes when input signals are large. When vin+ >>0 (vin-<<0) is large positive (negative), M1 is on and M2 is off. Hence ISD1=ISD5, since ISD2=0. The current flows through M3 which is then mirrored to M4, therefore ISD1=IDS3=IDS4=ISD5. The current in the compensation capacitor can only flows through M4, since M2 is off and the input impedance of the second stage A2 is ∞. That is ICc=IDS4=ISD5. On the other hand, when vin+<<0 (vin->>0) is large negative (positive), M1 is off and M2 is on. Hence, ISD1=0 which flows through M3 and mirrored to M4, therefore IDS3=IDS4=0. That is, current source ISD5 flows through M2, then to Cc directly, since M4 is off. In both cases, the maximum current that flows through Cc is ISD5. The output voltage of the opamp is approximately equal to v2, since A3≅1.
Cc
2ICcI
tCcq
t)(V
=SR SD1SD5o ==
=d
d
dd
1.3. OpAmp First Order Model
The objective of compensation is to make the opamp to behave as a single pole in the frequency of interest. That is, at least within the unity gain bandwidth frequency, wGB. The desired transfer function is
3
1
VO
ps1
A=Av(s)
+
where: AVO is the dc gain of the opamp, and p1 is the real axis dominant pole.
DB
w
AVO
wBW=p1 wGB
-20db/dec
Figure 5. Bode Plot of Opamp First Order Model The relation between the unity gain bandwidth, wGB, and the dominant pole p1 can be obtained by the finding the radian frequency when the magnitude of the voltage gain is equal to 1. That is,
1
pw
j
A
pw
j+1
A)Av(jw
1
GB
VO
1
GB
VOGB =≅=
1VOGB pAw ≅ At midband frequency, the gain is approximately given by :
s
ws
pA
ps
A
ps+1
A=Av(s) GB1VO
1
VO
1
VO ==≅
1.4. An Opamp with Feedback
4
Av(s) VoVin+
B
Figure 6. Ideal Feedback Configuration.
V A V A VO V in V= − Oβ V A AO V V( )1+ = Vinβ
Hence, the closed loop response is given by:
GB
GB
GBCL
ws1
11/sw+1
/swAv(s)+1
Av(s))s(A
ββββ +
===
where: (1/β) is the dc gain of the closed loop system. LG(s)=βAv(s) is the loop gain. The frequency when the closed gain is 3 Db down occurs when the LG becomes unity. That is,
1jww
LG(s)3db-
GB == β
That is, 1 ; www GBGB3db- === ββ 1.5. Settling Time Determination Opamps are compensated to behave as a simple pole system up to a radian frequency of wGB. This is the case whenever the PM of the Opamp is designed for at least 60°. The settling time is the time needed for the output of the opamp to reach a final value to within a predetermined tolerance. This can be determined using the first order model of the opamp given by:
)p
(1
A)(A
1
VOV ss
+=
The unity feedback (β=1) closed loop gain is given by:
5
1VO
1
VO
VO1VO
VO
1VOVOVO
1
VO
V
VCL
pA1
)A
11(
)A
11(pA1
A11
1
pA)
A11(
1
Ap
1
A)(A1
)(A)(A
ss
sssss
+
+≈
++
+=
++=
++=
+=
−
The step response is obtained as follows:
)pA
1(
)A
11()U()(A)(V
1VO
1
VOCLO ss
sss+
+==
−
Taking the inverse Laplace Transform, one gets,
ε−=−=+=∞
−+=
−
−−
1A
11)A
1(1)(V
u(t))1()A
1(1t)(V
VO
1
VOO
tw1
VOO
GBe
For large AVO,
ε−=∞≈−=
−=−
−
1)(V)1()t(V
u(t))1(t)(V
Otw
sO
twO
sGB
GB
e
e
Solve for ts in term of ε
)1ln()1ln(pA
1)1ln(w
1)(t1VOGB
s ετ
εεε ===
For a step input the output initially slews, then slowly settles toward its final value, determined by the gain bandwidth product. ε ts (settling time) <1% 4.6τ ≅ 5τ <.5% 5.3τ ≅ 6τ
6
1.6. Opamp Second Order Model
For compensation of an Opamp, we need at least a second order model
)s/p1)(s/p+(1
A=Av(s)
21
VO
+
DB
w
AVO
p1 wGB
-20db/dec
p2
-40db/dec
Figure 7. Bode Plot of Opamp Second Order Model. For frequency w>>p1, the model reduces to:
)s/p1(s
w)s/p1(s
pA)s/p1)((s/p
AAv(s)
2
GB
2
1VO
21
VO
+=
+=
+≅
The loop gain for this second order model is given by:
)s/p1(s
w=Av(s)=LG(s)
2
GB
+β
β
The radian frequency at 3db down is obtained by setting the magnitude of LG(s) to 1.
7
1)/pjw1(jw
w=)LG(jw
23db-3db-
GB3db- =
+β
When p2>>w-3db, then
1 ; ww
)p/w(1w
=w 3db-3db-2
23db-3db-
GB ==≅+ βββ
Phase margin is the phase angle between the loop gain phase angle and -180 degree. It is a measure of stability. First let us determine the loop gain phase angle:
)jw/p+(jw)(1
w=LG(jw)
2
GBβ
)w/p(tan-90=LG(jw))( 2
-1−Θ o
The phase margin is computed as follows: )/pw(tan90=(-180)-))LG(jw(=PM 23db-
-13db- −Θ o
PM)tan(90pw 23db- −= o
The closed loop gain is given by:
2
21VOVO
21
CL0CL
s)pp)(A1(
1+sA1
)p/1(1/p+1
AAv(s)+1
Av(s))s(A
βββ
+++
==
where:
1A ;1A+1
AA VO
VO
VOCL0 >>≅=
ββ
Comparing with general second order transfer function:
2
200
VO2
s)(w
1+sQw
1+1
A=s)(H
where: wo is the resonant frequency, and Q is the Q factor. We obtain, 2GB21VO0 pw)pp)(A+(1w ββ ≅=
8
2
GB
2
1VO
22
1
1VO
21
21VO
21
21VO
21
VO0
pw
ppA
)ppp(
)pA1(
)p(p)pp)(A+(1
)p/1(1/p)pp/()A+(1
Q
)p/1p/1(A1
Qw
βββ
ββ
β
=≅+
+=
+=
+=
++
=
The step response overshoot is a function of Q,
1Q4 2
100=overshoot% −
−π
e That is, when Q=0.5 there is no overshoot (%overshoot=0). In addition, wo = w-3db and PM≈65° PM wp2/wGB Q %overshoot 55° 1.4285 0.925 13.3% 60° 1.733 0.817 8.7% 65° 2.1459 0.717 4.7% 70° 2.748 0.622 1.4% 75° 3.733 0.527 0.008% For no overshoot, select PM=75°. Note that Q is proportional to β. That is the worst case PM occurs when β=1. Thus for opamp compensation where 0<β(s)<=1 is frequency dependent , if the opamp is compensated for β=1, it is guaranteed to be stable for all other β. 1.7. Small Signal Equivalent Circuit
9
V- V+
Y c (9)(6)
(7)
(1) (2)
(5)
(3) VDD
(4) VSS
M1 M2
M3 M4
M5
M6
M7
Figure 8a. Schematic Diagram of Unbuffered Opamp Circuit.
10
g ds2
g ds4
g ds6
g ds7
+
-
Vo
+
-
YC
V1a=vid
g ds2
g ds4
g ds6
g ds7
+
-
Vo
+
-
YC
V1a=vid
g m2V
1a
g m6V
1b
V2a=V1b+
-
g m1V
1a
V2a=V1b
+
-
g m6V
1b+
-
V1a=vid
+
-
g m2V
1a
g m6V
1b
V2a=V1b+
-R1 C1 R2 C2V2b=Vo
(a)
(b)
(c)
YC
Vx
Vx
Vx
I3
I2I1
V1 V2
+ +
Y1
Y3
Y2
g m2V
1
VX
g m6V
X
(d)
C2C1
C1
C2
Figure 8. Opamp Small Signal Equivalent Circuit of the First Two Stages. In Figure 8(a) each amplifier stage is replaced by its equivalent circuit. C1 and C2 are the parasitic capacitances of the Opamp at node 6 and 9 respectively. The second stage of an opamp is an inverter stage. The overall gain of the opamp can be made positive, by switching the positive and negative inputs of the differential gain stage. That is the positive input is now the gate of M2. Figure 8(b) shows this by reversing the polarity of the first controlled current source and replacing gm1 by gm2 to indicate M2 gate is the positive input. Figure 8(c) simplify the equivalent circuit by combining the resistances and capacitances.That is,
11
DS676ds7ds62
SD242ds4ds21
I)(1
gg1R
I)(1
gg1R
λλ
λλ
+=
+=
+=
+=
From Figure 8(c), the port current equations are derived to obtain the Y parameters:
x3m6232x2322xm62
1
)VY-(g)VY(Y)V-(VYVYVgI0I
++=++==
At node xV
231
31
31
m2x
231m2x31
2x31m2x1
x3
x13
2x31m23
VYY
YV
YYg-V
0VY-Vg)VY(Y0)V-(VYVgVY
,Vfor solve and I SubstituteVYI
0)V-(VYVgI
++
+=
=++=++
==++
Substituting to xV 2I
231
3m63231211
31
m2m63
231
31
31
m23m62322
VYY
YgYYYYYYV
YY)gg-(Y
VYY
YV
YYg-)Y-(g)VYY(I
++++
++
=
+
++
++=
The resulting Y-parameter matrix is
323121
31
3m6
31
m2m63
YYYYYY whereYY
YgYY)gg-Y(
00Y
++=∆
++∆
+=
The voltage gain is
3m6
m23m6
L22
21
1
2v Yg
)gY-g(Yy
y-VVA
+∆=
+==
12
Case1: 0Cor 0,Y c3 ==
21
222
111
YYsCGYsCGY
=∆+=+=
Solving for the voltage gain,
)CsR1()CsR1(GGgg
)sCG()sCG(gg
YYgg
Yg)gY-g(
Yyy
VVA
221121
m6m2
2211
m6m2
21
m6m2
3m6
m23m6
L22
21
1
2v ++
=++
==+∆
=+
−==
)ps-(1)
ps-(1
As)CR+s)(1CR+(1
RRggA
21
V0
2211
21m2m1v ==
where: 21m2m1V0 RRggA =
11
1 CR1p −
=
22
2 CR1p −
=
Case2: C33 sCsCY ==
323221C
2C31232121
3223112211323121
CCCCCC wheres)]sC(CG)C(C[GGG
)sC()sCG()sC()sCG()sCG()sCG(YYYYYY
++=∆∆+++++=
++++++=++=∆
Solving for the voltage gain,
C212
321m6131232
m6
321m6m2
3m62
C31232121
m23m6
3m6
m23m6v
RRs]CRRg)RC(C)RCs[(C1
)gC
s-1(RRgg
Csgs)]sC(CG)C(C[GGG)gsC-g(
Yg)gY-g(
A
∆++++++=
+∆+++++=
+∆=
Compare the denominator with,
21
2
121
2
2121 pp1s
p1s1
pp1s)
p1
p1s(1)
ps-(1)
ps-(1=D(s) +−≅++−=
13
C21m6C21m61C12C2
1 CRRg1
CRRgR)C(CR)C(C1p −
≅++++
−≅
L21C12L
m6
2
m6
C1C221
Cm62 C C C C C C ;
Cg
Cg
CCCCCCCg-
p ≈>>>>−
=−
=++
≅
C
m61 C
gz =
AV0-20db/dec
-40db/dec
-20db/dec
wp1 p2 zwGB
Figure 9. Bode Plot of Second Order System with RHP zero For good stability a phase margin of at least 60° is desirable This can be achieved as follows:
GB
V01V0GB
w10zA ;pAw
≥∞≈=
Then
14
m2C
Lm6
GB2
gCC2.2g
orw2.2p
=
=
This is shown below: That is, the transfer function has two poles and one RHP zero. The RHP zero contributes a negative phase angle.
)p
1)(p
1(
)z
1(A)(A
21
V0
V ss
s
s++
−=
The phase angle at the unity gain radian frequency (wGB) is
)p/w(tan)p/w(tan)/w(tan)w(A 2GB1
1GB1
GB1
GBV−−− −−−=∠ z
The phase margin PM is given by:
m2C
Lm6
C
m2
L
m6
GB2
2GB1
2GB1
2GB1
V011-
2GB1
1GB1
GB1
GBV
gCC2.2g
Cg2.2
Cg
2.2wp3.24)p/w(tan
)]p/w(tan907.5[180)]p/w(tan)A(tan)1.0([-tan180 60
)]p/w(tan)p/w(tan)/w(tan[180)w(A180PM
=
=
==
−−−+≈−−+=
=−−−+=∠+=
−
−−−
−−−
o
ooo
z
To achieve the assumption z=10wGB , the compensation capacitance Cc must be selected properly.
LC
m2C
Lm6
C
m2
L
m6GB2
m2m6C
m2
C
m6GB
0.22CC Combining
gCC2.2g
Cg2.2
Cg
;2.2wp
10gg Cg
10Cg
;10wz
≥
>⇒>>
=⇒==
In addition, LCC
m6
L
m62 CC
Cg
Cgzp <⇒<⇒< . Hence,
LCL CC0.22C <<
Case 3: 33
333
CC33333 sCG
CsGY ;
sC1
G1
sC1
G1
sC1RZ
+=+=+=+=
15
323121C
323121G
33
3321
2321312C1322313G321
33
3322
33
33112211
323121
CCCCCCGGGGGG
:wheresCG
sCCC)sCCGCCG(G)sCGGCGGC(GGG
sCGCsG
)sC(GsCGCsG
)sC(G)sC)(GsC(G
YYYYYY
++=∆++=∆
++++∆+++∆+
=
+
++
+
++++=
++=∆
{ }
321321
32323131C21
33321m6131232
32m6
3333m6m1
V
321321
32323131C21
321m611223321
32321
3m6
333m63m6m1
3321
2321312C33m61322313G321
m1333m63m6
33
33m6
m133
33m6
3m6
m13m6V
CCCRRRa'CCRRCCRRRRb'
CRCRRg)RC(C)RC[(Cc':where
sa'sb'sc'1
sgC
-CR1RggA
CCCRRRa]CCRRCCRRR[Rb
]CRRgCRCR)CRRR[(c:where
asbscs1GGG
sGg
CG-Cg1Ggg
sCCC)sCCGCCG(G)sCGgCGGCGGC(GGG)s]gCG-C(gG[g
sCGCsG
g
)gsCGCsG
-g(
Yg)gY-g(
A
=++∆=
+++++=
+++
+
=
=++∆=
+++++=
+++
+
=
+++∆++++∆++
=
++∆
+=
+∆=
2.0Opamp Design Specification
16
M10w=300ul=6.6u
M1w=36.6ul=6.6u
M2w=36.6ul=6.6u
V- V+
M5w=30ul=6.6u
M7w=90ul=6.6u
Cc
M3w=5.4ul-6.6u
M4w=5.4ul-6.6u
M6w=32.4ul=6.6u
M9w=300ul=6.6u
M8w=873.6ul=6.6u
Vo(10)
(9)(6)
(7)
(1) (2)
(8)
(5)
(3) VDD
(4) VSS
IB=100uA
Figure 10 Vdd =+5V, Vss=-5V, Ao>=15,000, GB=2π(5MHz), SR = 10V/uS, Ro ≤ 1.46k -4.5 <=CMR<=3, PM>60° SPICE Parameters: Kn=40uA/V2 , Kp=15uA/V2, λ=0.02 (1) Determine ID5 from the SR specification.
Let Cc=1pF
C
SD5
CI
=SR
uA52uA10
2I
II
333.56)(0.5)-E15(
6)-E10(2VK
I2LW
0.5|-1|3.5--5|V|-V-V|V|-VV10uA12)-6)(1E-(10E)SR)(C(I
SD5SD2SD1
22SD5(SAT)P
SD5
5
TP0biasDDTP0SG5SD5(SAT)
CSD5
====
===
=======
(2) Determine (W/L)1 from the wGB and positive CMR specifications
17
From wGB specification,
31.4umho5E6)12)(2-E1(wCg
IW/L)(K2C1
Cg=w
GBCm1
SD11PCC
m1GB
===
=
π
57.66)-6)(5E-2(15E
6]-31.4E[IK2)g(
LW 2
SD1P
2m1
1
===
From the positive CMR specification,
G1(max)SD5(SAT)DDSG1
SG1SD5(SAT)DDG1(max)
V-V-VV
V-VVV
=
−=
From the gate bias, Vbias, VSD5 can be determined.
666.26)(0.5)-E15(
6)-E5(2VK
I2LW
0.5|-1|1.5-|V|-VV
5.135.05V-V-VV
22SD1(SAT)p
SD1
1
TP0SG1SD1(SAT)
G1(max)SD5(SAT)DDSG1
===
===
=−−==
To satisfy both specifications select the higher (W/L) ratio. For matching and symmetry, we also choose (W/L)2 = (W/L)1=6.57 (3) Determine (W/L)3=(W/L)4 ratio from negative CMR
422
SSG1(min)N
DS3
3 LW1
(-5))-6)(-4.5-(40E6)-E5(2
)V-V(KI2
LW
====
(4) Determine (W/L)6 from the PM>60 specification. )p/w(tan-z)/w(tan-90PM 2GB
-1GB
-1=
21C221
m6 2
C
m6
C
m2GB CCC since ; pz ;
CCg
p ; Cg
z ; Cgw +><
+===
A pessimistic estimate of PM is obtained by assuming 2pz = . That is,
18
−
>
−
<
−<
−=
<
2PM90tan
gg
2PM90tan
gg
2PM90
ggtan
ggtan290
/Cg/Cg
2tan-90PM
m2m6
m6
m2
m6
m21-
m6
m21-
Cm6
Cm21-
To achieve PM>60,
6-120E6-E122.11760)/2)-tan((90
6E4.31g m6 ≈=−
>
From step 4 VDS6(SAT) =VDS3(SAT) =0.5V
66)(0.5)-E40(
6-E120VKg
LW
DS6(SAT)N
m6
6
===
The current through M6 is given by
uA306)(6)-E40(26)-E120(
W/L)(2Kg
I2
6N
2m6
DS6 ===
For balance condition the current through M6 must be properly ratioed with the current through M3,
30uAuA)5(16I
(W/L)W/L)(
I DS33
6DS6 ===
(5) Determine (W/L)7 from the balance condition and that ISD7=IDS6
16999.15)333.5(uA10uA30W/L)(
II
(W/L) 5SD5
SD77 ≈===
(6) DC gain AVO is computed and compared with the specification:
000,15700,156)-.02)(30E6)(.02-E5)(02.02(.
6)-6)(120E-(31.4E
I)(I)(gg
)gg)(g(ggg
RRggADS676SD242
m6m2
ds6ds5ds4ds2
m6m221m6m2V0
≥=++
=
++=
++==
λλλλ
19
(7) From the output resistance specification Ro ≤ 1.46k, (W/L)8 can be determined. The output resistance is given by:
SD88PSD88m8
O I(W/L)K21
I21
g1R ===
β
Solving for (W/L)8 , assuming ISD8 = 100uA and Pspice parameter KP=15 uA/V2
1566)-E100(3)+6)(1.46E-E15(2
1IRK2
1(W/L) 2SD8
2OP
8 ===
(8) Determine the (W/L) of the current mirrors. First set up the current source M10 to 100uA using the biasing current source IB. The VGS8 is set up to guarantee it operates at saturation by adding -0.5v beyond its threshold voltage of Vtp=-1v . That is VSG10 = 1.5v. (W/L)10 can now be determined as follows:
33.53(-1))-6)(1.5-(15E
6)-E100(2|)V|V(K
I2W/L)( 22
tpSG10P
SD1010 ==
−=
The rest of current sources are determined by proportionality as follows: ISD9 = 100uA = > (W/L)9 = (W/L)10(ISD9/ISD10) = (53.33)(100uA/100uA)=53.33 This complete the design. The results is summarized in the following table: PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 I(Ua) 5 5 5 5 10 30 30 100 100 100 T P P N N P N P P P P W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33 W(u) 36.792 36.792 5.6 5.6 29.865 33.6 89.6 873.6 298.65 298.65 L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6
Finding the W, L to the nearest multiple of λ=0.6 length. PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 I(Ua) 5 5 5 5 10 30 30 100 100 100 T P P N N P N P P P P W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33 W(u) 36.6 36.6 5.4 5.4* 30* 32.4* 90* 873.6 300 300 L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6
20
* Adjusted to satisfy the balance condition to minimize the input offset voltage, Vos:
6630902
4.54.32
(W/L)W/L)(
2(W/L)W/L)(
5
7
4
6
=
=
=
3.0 Opamp Simulation 3.1. DC Offset Voltage and Differential Gain Determination * Filename="opamp11.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC 0V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for OpAmp Offset Measurement M1 7 1 5 5 PMOS1 W=36.6U L=6.6U M2 6 2 5 5 PMOS1 W=36.6U L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6 4 4 NMOS1 W=32.4U L=6.6U M7 9 8 3 3 PMOS1 W=90U L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U Cc 9 6 1pF *Bias current IB 8 4 100UA * SPICE Parameters
21
.MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 *Analysis .OP .DC VID -300uV 300uV .1uV .TF V(10) VID .PROBE .END NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 0.0000 ( 2) 0.0000 ( 3) 5.0000 ( 4) -5.0000 ( 5) 1.3115 ( 6) -3.4878 ( 7) -3.4878 ( 8) 3.5084 ( 9) -1.1378 ( 10) .1495 ( 11) 0.0000 ( 12) 0.0000
The output voltage Vo=V(10) is 0.145V at quiescent operating point. This non-zero output voltage can be corrected or reduced by applying an input offset voltage, Vos. This offset is determined by finding the value of VID that makes the output
22
voltage Vo=V(10)=0. From the above graph, this is equal to –8.2484uV. The resulting output voltage from simulation is –2.753E-6V, as shown below: Modify the VID line in the netlist as follow: VID 11 0 DC –8.2484uV NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000 ( 5) 1.3115 ( 6) -3.4864 ( 7) -3.4878 ( 8) 3.5084 ( 9) -1.2881 ( 10)-2.753E-06 ( 11)-8.248E-06 ( 12) 0.0000 The differential gain can be obtained from the DC transfer characteristic by locating two points centered about the bias point of Vid=Vos=-8.2484uV. For accuracy, the two points must be far apart. From the graph:
4E833.16)-(-169.4E-6)-E5.225(
)8356.2(4048.4A vd +=−−
=
This is very closed to the value obtained using TF analysis of 1.810E+4, as shown below: **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 1.810E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03 3.2. Common-mode Voltage Range Determination * Filename="opamp24.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC –8.2484uV E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Measuring Input CMR M1 7 1 5 5 PMOS1 W=36.6U L=6.6U M2 6 2 5 5 PMOS1 W=36.6U L=6.6U
23
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6 4 4 NMOS1 W=32.4U L=6.6U M7 9 8 3 3 PMOS1 W=90U L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U Cc 9 6 1pF * Bias current IB 8 4 100UA * SPICE Parameter .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .DC VIC -5V 5V .05V .TF V(10) VIC .PROBE .END
24
The common-mode input range is determined when the output cease to follow the input linearly. At the low end, it determines VG1(min)=-4.4255, and at the high end, it determines VG1(max)=3.1383. These are very closed to the corresponding design specifications of VG1(min=-4.5 and VG1(max)=3. The common-mode gain is obtained by locating two points as far apart in the linear range about the operating point. This is shown in the graph above, and computed as follows:
49373.0)3192.4(1915.3)0677.2(6406.1Acm =
−−−−
=
This is very closed to the value obtained using the TF analysis of 0.4984, as shown below: **** SMALL-SIGNAL CHARACTERISTICS V(10)/VIC = 4.984E-01 INPUT RESISTANCE AT VIC = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03 The common mode reject ration CMRR is calculated as follows:
5.3712549373.0
4E833.1AA
CMRRcm
vd =+
==
3.3. Opamp Frequency Response * Filename="opamp33.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC –8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W=36.6U L=6.6U M2 6 2 5 5 PMOS1 W=36.6U L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6 4 4 NMOS1 W=32.4U L=6.6U M7 9 8 3 3 PMOS1 W=90U L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U
25
Cc 9 6 1pF CL 10 0 2pF *Bias current IB 8 4 100UA * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .PROBE .END
Pspice simulation results:
M16.5f ; 63PM ; 4E810.1A GBVO ==+= o **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 1.810E+04 INPUT RESISTANCE AT VID = 1.000E+20
26
OUTPUT RESISTANCE AT V(10) = 1.342E+03 The theoretical bandwidth and gain bandwidth are calculated as follows:
M3.222
E61402zf
E614012)-E1(
6)-E140(Cg
z
M5)318)(15700(fAf
Hz3182
20002pf
200012)-14E6)(1E6)(5E6)(.7-E140(
1CRRg
1-p
M714.6)-E35)(02.02(.
1I)(
1R
M56)-E5)(02.02(.
1I)(
1R
umho140gumho4.31g
z
C
m6
1V0GB
11
C21m21
6762
2421
m6
m2
===
===
===
===
=−
=≅
=+
=+
=
=+
=+
=
==
ππ
ππ
λλ
λλ
Simulation results are : f1 =258Hz, fGB=5.16M, fz and f2 are difficult to obtain accurately from bode plot. 3.4. Slew Rate Measurement * Filename="opamp44.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signal VIN 2 0 PWL(0,-5V 10us,-5V 10.01us,5V 30us, 5V 30.01us,-5V 1s, -5V) *Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Slew Rate Measurement M1 7 1 5 5 PMOS1 W=36.6U L=6.6U M2 6 2 5 5 PMOS1 W=36.6U L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6 4 4 NMOS1 W=32.4U L=6.6U M7 9 8 3 3 PMOS1 W=90U L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U Cc 9 6 1pF * Bias current IB 8 4 100UA
27
* External Component for Slew Rate Measurement VSH 1 10 DC 0V * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 *Analysis .TRAN .1ns 40us .PROBE .END
The positive slew rate is the slope of the rising edge of the output. This is computed from the two points on the rising edge. That is,
V/us 96.7085.10931.10
)2985.3(4386.3SR =−−−
=+
Similarly, the new slew rate is computed as follows:
28
V/us 55.10014.30619.306491.37368.2SR - −=
−−−
=
4.0 Op Amp Design Specification Vdd =+5V, Vss=-5V, Ao>=30,000, GB=2π(5MHz), SR = 10V/uS, Ro ≤ 1.46k -4.5 <=CMR<=3 SPICE Parameters: Kn=40uA/V2 , Kp=15uA/V2, λ=0.02 Increasing Overall DC Gain DC gain AVO is computed and compared with the specification:
000,30700,156)-.02)(30E(.02
6)-(120E6)-E5)(02.02(.
6)-(31.4E
I)(g
I)(g
)gg(g
)g(gg
]R][gRg[AAA
DS676
m6
SD242
m2
ds6ds5
m6
ds4ds2
m22m61m2V2V1V0
≤=
+
+
=
+
+
=
+
+
===
λλλλ
Pspice simulation results:
M16.5f ; 63PM ; 4E810.1A GBVO ==+= o Increasing Overall Gain By Increasing A V1
SD2
2
42
P
SD242
SD22P
SD242
m2V1 I
(W/L))(
2KI)(
I(W/L)2KI)(
gAλλλλλλ +
=+
=+
=
The current I is half the bias current and is independent of ( . That is, the gain can be
adjusted by simply adjusting while remains constant. The gain is proportional to SD2 SD5I
I2W/L)
2W/L)( SD2 V1A
2(W/L) . For example to increase the overall gain by 2, one needs to increase (W/L) by a factor of 4.
21 (W/L) ,
PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 I(Ua) 5 5 5 5 10 30 30 100 100 100 T P P N N P N P P P P
29
W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33 W(u) 4*36.6 4*36.6 5.4 5.4 30 32.4 90 873.6 300 300 L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 Increasing Av1 * Filename="opamp331.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Increasing Overall Gain By Increasing W/L of M1 & M2 * Input Signals VID 11 0 DC –8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U M2 6 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6 4 4 NMOS1 W={32.4U} L=6.6U M7 9 8 3 3 PMOS1 W={90U} L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U Cc 9 6 1pF *Bias current IB 8 4 100UA * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .AC DEC 10 0.1HZ 10000MegHz
30
.TF V(10) VID
.PROBE
.END Before increasing (W/L) of M1 and M2 **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 1.810E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03 After Increasing (W/L) of M1 and M2 by 4 **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.590E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03
Although the DC gain increases the PM decreases.
31
AV0=3.590E+4; PM=29°; fGB=10.596M The Overall Gain Is Independent of V2A The second stage gain can not be used to increase the overall gain but is used to adjust the phase margin as shown below:
DS6
6
76
N
DS676
DS66N
DS676
m6V2 I
W/L)()(
K2I)(
IW/L)(K2I)(
gA
λλλλλλ +=
+=
+=
Since is determined by current mirror, increasing ( increases I proportionately as shown below:
DS6I 6W/L) DS6
constantI
W/L)(I
(W/L) I
(W/L)W/L)(
IDS4
4
DS6
6DS4
4
6DS6 ==⇒=
That is, increasing or does not increase the overall gain, but g is increased by DS6I 6W/L)( m6
DS66 IW/L)(
DS6I. That is, g is doubled by increasing ( by a factor of 2, and by current mirror
is also increase by a factor of 2. Similarly, ( must be doubled, since I = . The phase
margin, which deteriorates when increasing (W/L) or g , can be compensated by increasing .
m6 6W/L)
m2
7W/L)
2
DS6 DS7I
m6g PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 I(Ua) 5 5 5 5 10 2*30 2*30 100 100 100 T P P N N P N P P P P W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33 W(u) 4*36.6 4*36.6 5.4 5.4 30 2*32.4 2*90 873.6 300 300 L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 Pspice simulation results:
M7.9f ; 51.3PM ; 4E590.3A GBVO ==+= o **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.590E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03
32
The phase margin can be increased further by increasing both ( and . The desired phase
margin of 65° is approached when and ( are increased by a factor of 4 6W/L) 7W/L)(
6W/L)( 7W/L) PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 I(Ua) 5 5 5 5 10 4*30 4*30 100 100 100 T P P N N P N P P P P W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33 W(u) 4*36.6 4*36.6 5.4 5.4 30 4*32.4 4*90 873.6 300 300 L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 The Overall Gain Is Independent of But Adjust Phase Margin V2A * Filename="opamp331.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Increasing Overall Gain By Increasing W/L of M1 & M2 * Input Signals VID 11 0 DC –8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT
33
* Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U M2 6 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6 4 4 NMOS1 W={4*32.4U} L=6.6U M7 9 8 3 3 PMOS1 W={4*90U} L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U Cc 9 6 1pF *Bias current IB 8 4 100UA * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .PROBE .END Pspice simulation results:
M17.9f ; 61.5PM ; 4E590.3A GBVO ==+= o **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.590E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03
34
5.0 Phase Margin Correction By Moving the Zero from RHP to LHP The location of zero is given by:
)Rg1(C
1
)Rg1(C
1zC
m6C3
m63 −
=−
=
The zero can be moved from the RHP to the LHP by selecting m6
C g1R >> , with this choice the zero
is approximately given by:
CCCR1-z ≈
A zero in the LHP increase the phase margin rather decrease as in the case of RHP zero. The transfer function of an op amp compensated by resistor R and capacitor connected in series is given by: C CC
35
−
−
−
=
321
V0
V
ps1
ps1
ps1
zs-1A
s)(A
where:
CC
1C3
21
m62
C21m61
CR1 z
CR1p
CCg
p
CRRg1p
−≈
−≈
+−
≈
−≈
321
21
V0
V p p p since ;
ps1
ps1
zs-1A
s)(A <<<<
−
−
≈
−
−
+=∠+=
−
−
=∠
2
GB1-
1
GB1-GB1-oGBV
o
2
GB1-
1
GB1-GB1-GBV
pw
tanp
wtan
zw
tan180)w(A180PM
pw
tanp
wtan
zw
tan)w(A
With extra phase margin introduced by the LHP zero, the phase margin can be increased without increasing the sizes of M6 and M7. To make sure that the op amp behaves as single order system within the gain bandwidth, . One positions the zero 20% (GBw GB1.2wz = ) over the gain bandwidth. In the
previous example, the non-dominant pole was position at p . Where w is the
original gain bandwidth prior to doubling g which double the gain bandwidth. The new phase margin gain be calculated as follows:
'GBGB w2.2=2 1.1w= '
GB
m2
( ) ( ) ( ) 53.87909.0tanAtan833.tan180
1.1ww
tanp
pAtan
1.2ww
tan180
pw
tanp
wtan
zw
tan180)w(A180PM
1-V0
1-1-o
GB
GB1-
1
1V01-
GB
GB1-o
2
GB1-
1
GB1-GB1-oGBV
o
≈−−+≈
−
−
+=
−
−
+=∠+=
36
The value of to place the zero is calculated as follows: CR
k25.136)-x31.4E2(2.1
1g2.11R
Cg2.1w2.1
CR1z
m2C
C
m2GB
CC
===
===
PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 I(Ua) 5 5 5 5 10 35 35 100 100 100 T P P N N P N P P P P W/L 6.57 6.57 1 1 5.333 7 18.665 156 53.33 53.33 W(u) 4*36.6 4*36.6 5.4 5.4 30 37.8 105 873.6 300 300 L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6
pF1C k,25.13R CC ==
M10w=300ul=6.6u
M1w=4*36.6ul=6.6u
M2w=4*36.6ul=6.6u
V- V+
M5w=30ul=6.6u
M7w=90ul=6.6u
Cc
M3w=5.4ul-6.6u
M4w=5.4ul-6.6u
M6w=32.4ul=6.6u
M9w=300ul=6.6u
M8w=873.6ul=6.6u
Vo(10)
(9)
(7)
(1) (2)
(8)
(5)
(3) VDD
(4) VSS
Rc(6b)(6a)
IB=100uA
Fig 10a * Filename="opamp33z.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals
37
VID 11 0 DC -8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U M7 9 8 3 3 PMOS1 W={90U} L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U Cc 9 6b 1pF Rc 6a 6b {13.25k} *Bias current IB 8 4 100UA * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .PROBE .END Pspice simulation results:
M294.10f ; 85.5PM ; 4E590.3A GBVO ==+= o **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.590E+04
38
INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03 NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000 ( 5) 1.1562 ( 7) -3.4870 ( 8) 3.5084 ( 9) -1.5153 ( 10) -.2260 ( 11)-8.248E-06 ( 12) 0.0000 ( 6a) -3.4842 ( 6b) -3.4842
6.0 Implementation of Rc with NMOS Transistor Transistor M11 has VDS11=0 since no dc bias current flows through its because of capacitor Cc. Therefore, it is operating at the ohmic or triode region. That is, DSDSTNGSND /2]VV-V-(W/L)[VKI = The resistance value implemented by this transistor is givcen by
39
[ ]
[ ] 65.1)6.0(2)5(4836.3()6.0(211
2V2VV FSBTOTN
=−−−−++=
−++= φφγ
uu
276276.0
1.65)-(-3.4842)-3)(56(13.25E-E401
)V(VRK1W/L)(
)V(W/L)(VK1
VIrR
TNGSCN
TNGSN
1
DS
DDS10C
==+
=−
=
−=
∂∂
==−
M10
VDD
VSS
M1 M2
M3 M4
M5 M7
M6
M9
M8
CcM11
VDD
(6a) (6b)
(8)
(1) (2)
V- V+
(5)
(7)
(4)
(3)
(9)
(10)
IB
* Filename="opamp33m.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC -8.2484uV AC 1V E- 1 12 11 0 -0.5
40
E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U M7 9 8 3 3 PMOS1 W={90U} L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U M11 6b 3 6a 4 NMOS1 W=6U L=27U Cc 9 6b 1pF *Rc 6a 6b {13.25k} *Bias current IB 8 4 100UA * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .PROBE .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .END Pspice simulation results:
M9.11f ; 87.7PM ; 4E590.3A GBVO ==+= o **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.590E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.342E+03
41
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000 ( 5) 1.1562 ( 7) -3.4870 ( 8) 3.5084 ( 9) -1.5137 ( 10) -.2244 ( 11)-8.248E-06 ( 12) 0.0000 ( 6a) -3.4843 ( 6b) -3.4843
42
7.0 Opamp with ClassAB Output Buffer
M10
VDD
VSS
M1 M2
M3 M4
M5M7
M6
M9
M8CcM11
VDD
(6a) (6b)
(8)
(1) (2)
V- V+
(5)
(7)
(4)
(3)
(9)
(10)
M12
M13
(13)
(14)
k*(W/L)p
(W/L)n
(W/L)n
(W/L)p
k*(W/L)n
I k*I
(W/L)p
IB
Figure 12b k=3 * Filename="op33zab2.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC -8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
43
M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U M7 14 8 3 3 PMOS1 W={90U} L=6.6U M8 4 9 10 10 PMOS1 W={3*90U} L=6.6U M9 3 14 10 4 NMOS1 W={3*32.4U} L=6.6U M10 8 8 3 3 PMOS1 W=300U L=6.6U M11 6b 3 6a 4 NMOS1 W=6U L=27U M12 9 9 13 13 PMOS1 W=90U L=6.6U M13 14 14 13 4 NMOS1 W=32.4U L=6.6U Cc 9 6b 1pF *Bias current IB 8 4 100UA * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .PROBE .DC VID -5V 5V .1V .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .END Pspice simulation results:
3E113.1R ; M9.10f ; 86.1PM ; 4E065.3A OGBV0 +==°=+= **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.065E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.113E+03 NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000 ( 5) 1.1562 ( 7) -3.4870 ( 8) 3.5084 ( 9) -3.5234 ( 10) -2.0125 ( 11)-8.248E-06 ( 12) 0.0000 ( 13) -2.0182
44
( 14) .6098 ( 6a) -3.4843 ( 6b) -3.4843
45
8.0 Process and Temperature Independent Opamp Design Using Widlar Current Source
VDD
VSS
(8)
(3)
Rb
MB1
MB2(W/L)p
MB3MB4
(W/L)n4(W/L)n
(W/L)p
(15)
(16)
I I
I
Msnk1(W/L)n
Msrc1(W/L)p
(4)
(5)
+Vsnk
Msnk22(W/L)n
I 2I
Msnk33(W/L)n
3I
+Vsrc
2I 3I
Msrc22(W/L)p
Msrc33(W/L)p
(2)
Figure 12
III D4D3 ==
bGS4GS3 IRVV += Subtracting the threshold voltage (neglecting body effect) from both sides, one obtains: TN0V
b4N3N
bTN0GS3TN0GS3
IRW/L)(K
I2W/L)(KI2
IRV-VV-V
+=
+=
46
Solve for Rb,
b4
3
3N
R(W/L)(W/L)
1I(W/L)K2
2=
−
or
34b
m3
b
4
3
m3
4(W/L)(W/L) If ;R1g
R(W/L)(W/L)
12g
==
−
=
Thus is determined by geometric ratio only. It is independent of power supply voltage, process parameter, and temperature. This is only true to the first order of approximation, since the body effect is neglected. In addition all other transconductance are also stabilized since all transistor currents are derived from the same biasing network. That is,
m3g
r transistochannel-pfor ;gI(W/L)KI(W/L)Kg
r transistochannel-nfor ;gI(W/L)I(W/L)
g
m3D33N
DiiPmi
m3D33
Diimi
=
=
Design a 10uA widlar current source with the minimum transistor sizes for biasing an opamp circuit. Assuming all transistors are of the same length L=6.6u. The minimum width corresponding to (W/L)=1 and 6.0=λ is obtained as follows:
5.4uW
12(0.5)-6.6u
W2LD-LW
LW
eff
≈
===
The minimum W for the widlar current source is 2(5.4u)=10.8u, since the differential amplifier input stage load current is half of the widlar design current value. The minimum pmos transistor (W/L) is calculated to achieve the same transconductance. That is,
30u28.8uu)8.10(15u
u40WKK
W
LW
KK
LW
NP
NP
NeffP
N
Peff
≈===
=
The widlar cu * Filename="op33zab4.cir" * Widlar Source = Supply Independent
47
* Input Signals * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT VSNK 5 0 DC 0VOLT VSRC 2 0 DC 0VOLT * Netlist for Frequency Response Measurement MB1 15 8 3 3 PMOS1 W=30U L=6.6U MB2 8 8 3 3 PMOS1 W=30U L=6.6U MB3 15 15 4 4 NMOS1 W={10.8U} L=6.6U MB4 8 15 16 4 NMOS1 W={4*10.8U} L=6.6U Msrc1 2 8 3 3 PMOS1 W=30U L=6.6U Msrc2 2 8 3 3 PMOS1 W={2*30U} L=6.6U Msrc3 2 8 3 3 PMOS1 W={3*30U} L=6.6U Msnk1 5 15 4 4 NMOS1 W=10.8U L=6.6U Msnk2 5 15 4 4 NMOS1 W={2*10.8U} L=6.6U Msnk3 5 15 4 4 NMOS1 W={3*10.8U} L=6.6U Rb 16 4 20K * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .PROBE .OP .DC VSNK -5V 5V .1V *.DC VSRC -5V 5V .1V .END
48
49
NAME MB1 MB2 MB3 MB4 Msrc1 MODEL PMOS1 PMOS1 NMOS1 NMOS1 PMOS1 ID -9.89E-06 -8.70E-06 9.89E-06 8.70E-06 -9.30E-06 VGS -1.46E+00 -1.46E+00 1.50E+00 1.33E+00 -1.46E+00 VDS -8.50E+00 -1.46E+00 1.50E+00 8.37E+00 -5.00E+00 VBS 0.00E+00 0.00E+00 0.00E+00 -1.74E-01 0.00E+00 VTH -1.00E+00 -1.00E+00 1.00E+00 1.11E+00 -1.00E+00 VDSAT -4.59E-01 -4.59E-01 4.99E-01 2.20E-01 -4.59E-01 NAME Msrc2 Msrc3 Msnk1 Msnk2 Msnk3 MODEL PMOS1 PMOS1 NMOS1 NMOS1 NMOS1 ID -1.86E-05 -2.79E-05 1.06E-05 2.11E-05 3.17E-05 VGS -1.46E+00 -1.46E+00 1.50E+00 1.50E+00 1.50E+00 VDS -5.00E+00 -5.00E+00 5.00E+00 5.00E+00 5.00E+00 VBS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 VTH -1.00E+00 -1.00E+00 1.00E+00 1.00E+00 1.00E+00 VDSAT -4.59E-01 -4.59E-01 4.99E-01 4.99E-01 4.99E-01
9.0 Inferred Biasing
50
VDD
VSS
(8)
(3)
Rb
MB1
MB2(W/L)p
MB3MB4
(W/L)n4(W/L)n
(W/L)p
(15)
(16)
I I
I
Msnk1(W/L)n
Msrc1(W/L)p
(4)
(5) +Vsnk
Msnk(W/L)n
I I
NOTE: V(5)=V(15)
(6)
Figure 12a * Filename="op33zab5.cir" * Widlar Source = Supply Independent * Input Signals * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT VSNK 6 0 DC 0VOLT * Netlist for Frequency Response Measurement MB1 15 8 3 3 PMOS1 W=30U L=6.6U MB2 8 8 3 3 PMOS1 W=30U L=6.6U
51
MB3 15 15 4 4 NMOS1 W={10.8U} L=6.6U MB4 8 15 16 4 NMOS1 W={4*10.8U} L=6.6U Msrc1 5 8 3 3 PMOS1 W=30U L=6.6U Msnk1 5 5 4 4 NMOS1 W=10.8U L=6.6U Msnk 6 5 4 4 NMOS1 W=10.8U L=6.6U Rb 16 4 20K * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .PROBE .OP .DC VSNK -5V 5V .1V *.DC VSRC -5V 5V .1V .END NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 3) 5.0000 ( 4) -5.0000 ( 5) -3.5010 ( 6) 0.0000 ( 8) 3.5413 ( 15) -3.5010 ( 16) -4.8260
52
53
VDD(3)
Rb
MB3MB4
(W/L)n4(W/L)n(16)
I
MB1
MB2(W/L)p
(W/L)p
I
+
MB3a(W/L)nMB4a
(W/L)n
Msnka(W/L)n
Msnkb(W/L)n
Vsnk
MB1a(W/.L)p
MB2a(W/L)p
(4) VSS
(2)
(15a)
(15b)
(8b)
(15a)
(15b)
8a)
(14)
(13)
(12)
10.0 Cascode Widlar Current Sink
54
Figure 12b * Filename="op33zab6.cir" * Widlar Source = Supply Independent * Input Signals * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT VSNK 2 0 DC 0VOLT * Netlist for Frequency Response Measurement MB1 13 8b 3 3 PMOS1 W=30U L=6.6U MB1a 15a 8a 13 13 PMOS1 W=30u L=6.6U MB2 8b 8b 3 3 PMOS1 W=30U L=6.6U MB2a 8a 8a 8b 8b PMOS1 W=30U L=6.6U MB3 15b 15b 4 4 NMOS1 W={10.8U} L=6.6U MB3a 15a 15a 15b 4 NMOS1 W=10.8U L=6.6U MB4 14 15b 16 4 NMOS1 W={4*10.8U} L=6.6U MB4a 8a 15a 14 4 NMOS1 W=10.8U L=6.6U Msnka 12 15b 4 4 NMOS1 W=10.8U L=6.6U Msnkb 2 15a 12 4 NMOS1 W=10.8U L=6.6U Rb 16 4 15.5K * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .PROBE .OP .DC VSNK -5V 5V .1V .TF V(2) VSNK .END **** SMALL-SIGNAL CHARACTERISTICS V(2)/VSNK = 1.000E+00 INPUT RESISTANCE AT VSNK = 1.489E+09 OUTPUT RESISTANCE AT V(2) = 0.000E+00
55
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 2) 0.0000 ( 3) 5.0000 ( 4) -5.0000 ( 12) -3.4910 ( 13) 3.4907 ( 14) -3.4842 ( 16) -4.8434 ( 8a) 2.0117 ( 8b) 3.5058 ( 15a) -1.3184 ( 15b) -3.4956
56
11.0 Opamp Design with Process and Temperature Independent Implementation 1
VDD
VSS
M1 M2
M3 M4
M5M7
M6
M9
M8CcM11
VDD
(6a) (6b)
(8)
(1) (2)
V- V+
(5)
(7)
(4)
(3)
(9)
(10)
M12
M13
(13)
(14)
k*(W/L)p
(W/L)n
(W/L)n
(W/L)p
k*(W/L)n
I k*I
(W/L)p
Rb
MB1
MB2(W/L)p
MB3MB4(W/L)n
4(W/L)n
(W/L)p
(15)
(16)
Figure 12c * Filename="op33zab3.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC -8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
57
M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U M7 14 8 3 3 PMOS1 W={90U} L=6.6U M8 4 9 10 10 PMOS1 W={3*90U} L=6.6U M9 3 14 10 4 NMOS1 W={3*32.4U} L=6.6U M11 6b 3 6a 4 NMOS1 W=6U L=27U M12 9 9 13 13 PMOS1 W=90U L=6.6U M13 14 14 13 4 NMOS1 W=32.4U L=6.6U MB1 15 8 3 3 PMOS1 W=30U L=6.6U MB2 8 8 3 3 PMOS1 W=30U L=6.6U MB3 15 15 4 4 NMOS1 W={10.8U} L=6.6U MB4 8 15 16 4 NMOS1 W={4*10.8U} L=6.6U Rb 16 4 19K Cc 9 6b 1pF * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .PROBE .DC VID -5V 5V .1V .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .END Pspice simulation results:
3E113.1R ; M43.9f ; 88.5PM ; 4E180.3A OGBV0 +==°=+= **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.180E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.133E+03 NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000
58
( 5) 1.1533 ( 7) -3.4964 ( 8) 3.5174 ( 9) -3.5295 ( 10) -2.0277 ( 11)-8.248E-06 ( 12) 0.0000 ( 13) -2.0334 ( 14) .5814 ( 15) -3.4753 ( 16) -4.8170 ( 6a) -3.4936 ( 6b) -3.4936
59
12.0 Opamp Design with Process and Temperature Independent Implementation 2
VDD
VSS
M1 M2
M3 M4
M5M7
M6
M9
M8
MB1(W/L)p
MB3a(W/L)n
MB3
MB2(W/L)p
MB4a(W/L)n
MB44(W/L)n
CcM11
Rb
(6a) (6b) (9)
(10)
(8)
(1) (2)
V+V-
(7)
(5)
(4)
(3)
(13)
(14)
(15)
(16) (W/L)n
Figure 12a * Filename="opamp33b.cir" * MOS Diff Amp with PMOS Input and Current Mirror Load * Input Signals VID 11 0 DC -8.2484uV AC 1V E- 1 12 11 0 -0.5 E+ 2 12 11 0 0.5 VIC 12 0 DC 0V * Power Supplies VDD 3 0 DC 5VOLT VSS 4 0 DC -5VOLT * Netlist for Frequency Response Measurement M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U M3 7 7 4 4 NMOS1 W=5.4U L=6.6U M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U M5 5 8 3 3 PMOS1 W=30U L=6.6U
60
M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U M7 9 8 3 3 PMOS1 W={90U} L=6.6U M8 4 9 10 10 PMOS1 W=873.6U L=6.6U M9 10 8 3 3 PMOS1 W=300U L=6.6U M11 6b 13 6a 4 NMOS1 W={20.4U} L=6.6U MB1 13 8 3 3 PMOS1 W=30U L=6.6U MB2 8 8 3 3 PMOS1 W=30U L=6.6U MB3a 13 13 14 4 NMOS1 W=10.8U L=6.6U MB3 14 14 4 4 NMOS1 W=10.8U L=6.6U MB4a 8 13 15 4 NMOS1 W=10.8U L=6.6U MB4 15 14 16 4 NMOS1 W=43.2U L=6.6U Cc 9 6b 1pF *External Bias Resistor Rb 16 4 {17.5K} * SPICE Parameters .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 * Analysis .DC VID -5V 5V .1V .AC DEC 10 0.1HZ 10000MegHz .TF V(10) VID .PROBE .END Pspice simulation results:
3E379.1R ; M65.8f ; 83PM ; 4E790.3A OGBV0 +==°=+= **** SMALL-SIGNAL CHARACTERISTICS V(10)/VID = 3.790E+04 INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(10) = 1.379E+03 NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 4.155E-06 ( 2)-4.155E-06 ( 3) 5.0000 ( 4) -5.0000 ( 5) 1.1520 ( 7) -3.5007 ( 8) 3.5216 ( 9) -1.5420
61
( 10) -.2603 ( 11)-8.310E-06 ( 12) 0.0000 ( 13) -1.3042 ( 14) -3.4895 ( 15) -3.4575 ( 16) -4.8343 ( 6a) -3.4979 ( 6b) -3.4979
[ ] [ ][ ] 64.1)6.0(2)5(4979.3()6.0(211
2VSS-V(6a)2V2V2VV FTOFSBTOTN
=−−−−++=
−++=−++= φφγφφγ
uu
6.64.204.3
1.64)-(-3.4979)-3)(-1.30426(13.25E-E401
)VV(6a))13(V(RK1W/L)(
)V)a6(V)13(W/L)(V(K1
)V(W/L)(VK1
VIrR
TNCN
TNNTNGSN
1
DS
DDS10C
≈=+
=−−
=
−−=
−=
∂∂
==−
62