and all constant susceptance circles above and below the circle b �0 correspond to b � 0 and b � 0, respectively.

Figure 4 shows the superimposed EOSC in which the constantconductance circle of x � 0 overlaps the constant susceptancecircle of b � 0.

To compare EOSC with different parameters, in Figure 5, weshow a superimposed EOSC for �1 � 2�/3, �2 � �5�/6, p � 0.5,which is another normal case of EOSC. Also, we can find theposition of point O is changed because �2 – �1 changes from 3�/2to �3�/2.The other EOSC characteristics are similar with theabove example of EOSC.

5. CONCLUSION

In this article, the LNTL model with active parameters is analyzedand to solve problems of LNTL with ACI and ALI, an extendedOSC is constructed by changing the parameters from the passivedomain to active one. Simulation results of several EOSC exam-ples are also showed for understanding and visualizing. Applica-tions of EOSC for active devices in RF engineering will be furtherinvestigated in the future.

ACKNOWLEDGMENTS

The authors would like to thank professor D. Torrungrueng inAsian University for providing us with the newest papers.

REFERENCES

1. W. Yongle, H. Haiyu, and L. Yuanan, An omnipotent smith chart forlossy nonreciprocal transmission lines (published online), MicrowaveOpt Technol Lett 49 (2007), 2392–2395.

2. P.H. Smith, Book review: Electronic applications of the smith chart,Microwave J 39 (1996), 178.

3. D. Torrungrueng and C. Thimaporn, A generalized zy smith chart forsolving nonreciprocal uniform transmission-line problems, MicrowaveOpt Technol Lett 40 (2004), 1, 57–61.

4. E. Gago-Ribas, C. Dehesa-Martinez, and M.J. Gonzalez-Morales, Com-plex analysis of the lossy-transmission line theory: A generalized smithchart, Turk J Electr Eng Comput Sci 14 (2006), 173–194.

5. W. Yongle, L. Yuanan, and L. Shulan, A dynamic smith chart based onlossy uniform transmission-line (accepted in chinese), Microelectronics,in press.

6. D. Torrungrueng, P.Y. Chou, and M. Krairiksh, An extended zy t-chartfor conjugately characteristic impedance transmission lines with activecharacteristic impedances, Microwave Opt Technol Lett 49 (2007),1961–1964.

© 2008 Wiley Periodicals, Inc.

AN EXPERIMENTAL LOAD MATCHINGTECHNIQUE FOR RF CMOS POWERAMPLIFIER

YunSeong Eo,1 Seung-Joon Lee,1 and Dong-Hyun Baek2

1 Electronic Engineering Department, KwangWoon University, 447-1Wolgye-dong, Nowon-gu, Seoul, South Korea 139-701;Corresponding author: yseo71@kw.ac.kr2 Electronic Engineering Department, Chung-Ang University, 221,Heukseok-Dong, Dongjak-gu, Seoul Korea 156-756

Received 5 September 2007

ABSTRACT: A load matching method for CMOS PA (power amplifier)design is proposed. The contours for RF power and efficiency can bedrawn while considering external L and C as tunable X and Y variables.On the basis of the existence of this contour, the realization of loadmatching of CMOS PA is easily achieved and optimized. A tested CMOSPA based on 0.18 �m CMOS technology shows a design example whoseP1dB is 17.8 dBm and power efficiency 37%, respectively. © 2008Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 899–902,2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23248

Key words: CMOS power amplifier; power matching

1. INTRODUCTION

Nowadays, the whole RF transceiver can be integrated on single Sichip based on CMOS device technology. However, the poweramplifier (PA) is still troublesome component to be integrated andthe high performance external PAs based on III-V compoundsemiconductor devices are widely used for most RF systemsrequiring comparably high power output level. Despite of difficul-ties of its integration, in order to reduce external components,system volume and cost, many circuit designers endeavor to inte-grate CMOS driver amplifiers and PA for moderate RF powerapplications [1–3]. In that case, most of PAs output load matchinghas been achieved through very laborious tuning because the loadpull experiment of CMOS device is very difficult with time-varying probe contact resistance and breakdown in high VDSregion, and the model based simulation also cannot consider ex-actly many parasitic effects due to package and lines on PCBboard. In this article, in order to cope with these design problems,a newly proposed experimental load matching technique adequateto CMOS PA and DA designs is presented. Similar to conventionaloutput load pull method, we show that a newly developed powercontour method makes it easy to tune PA load matching. And as anexperimental example a CMOS PA is implemented with 0.18 �mCMOS technology in this work.

2. THE PROPOSED LOAD MATCHING METHOD FOR PADESIGN

Using well-known load pull measurement, the RF power andefficiency optimal impedance points and contours can be obtained,

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Figure 5 EOSC (superimposed) for �1 � 2�/3, �2 � �5�/6, p � 0.5.[Color figure can be viewed in the online issue, which is available atwww.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 50, No. 4, April 2008 899

which depends on the real and imaginary parts of output loadimpedance. However, in most CMOS RF transmitter design, thedesigners have no load pull measurement data and have to designdriver or PA using only given CMOS transistor models. Moreover,unpredictable parasitic such as package and PCB effects causeserious mismatch between simulation and actual measurement.Therefore, after mounting the transceiver chip on PCB board, verydifficult and tedious tuning is left as final job. Because tuning isdone by changing and optimizing the external L and C compo-nents, if any power or efficiency contour can exist uniquely, it willgive us a convenience and systematic procedure for load matching.The Figure 1 shows an example of CMOS power amplifier includ-ing package parasitic such as pad capacitance and wire bondinductance. In this case, actually we can only change the values ofexternal L and C, and there may be one optimal set of L and Cvalues for optimal power matching. Hence, we simulate a PAwhose circuit schematic is like Figure 1 and calculate the outputRF power and efficiency for various L and C values. The Figure 2shows the simulated power contour when the values of L and C areconsidered as X-Y variables. As we expect, there is one poweroptimal point and around that point the power contour can bedrawn. Even though the simulated result may be very differentcomparing with experimental one due to unknown parasitic, wecan guess that there is also single optimal point in the experimentalpower contour. Therefore, in actual case we first try only 4 or 5

sets of LC values experimentally and the obtained results give usthe gradient vector of RF power and the LC value-area aroundwhich the optimal point may exist.

In this work, the proposed method is applied to one stagedifferential CMOS PA design. In spite of lower achievable powercompared with common source cell, the cascode transistor cell isused as PA core because the voltage swing between drain and gateof common source is very large up to 1–2 times VDD under largesignal operation. To prevent the gate oxide breakdown caused byhot carrier effect, the 3.3 V thick oxide NMOS is used as commongate transistor [4]. The gate length of thick oxide NMOS is 0.35�m. However, the common source NMOS is nominal thin oxideNMOS transistor in order to achieve high effective transconduc-tance and gain of cascode cell. The Figure 3 shows the schematicof CMOS PA core. The gate bias is applied through the highvalued resistors R2 and R3, and input RF bypass capacitor is alsointegrated on chip. The gate of common gate NMOS is biased atVDD with small valued resistor R1. The gate widths of CS NMOSand CG NMOS are 2048 �m (4 cell � 64 fingers � 8 �m) and2048 �m, respectively. The input port is matched for small signalgain with external passive components on PCB. To obtain theoptimal output power the input matching must be also optimizedfor RF power, however, the obtained output power when the inputis small signal matched has little difference from that of powermatching case.

The output load matching is composed of chip pad, bond wire,microstrip line on PCB, and LC passive components as shown inFigures 1 and 3. For the RF measurement, apparatus the differen-tial signal is converted to 50 � referenced single ended one usingexternal balun. The loss of balun is deembedded in power andefficiency calculation. For preventing ESD problem, gategrounded NMOS is shunt connected at the in/out pads.

3. IMPLEMENTATION AND EXPERIMENTAL RESULTS

A one stage 2.4 GHz CMOS power amplifier is designed andfabricated using 0.18 �m CMOS technology. To show a reason-able figure of power contour many sets of L and C values are triedand measured in this work. The scope of L value is from 1 to 8 nHas discrete value and for C the value varies from 1 to 5 pF. The

Amp

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Figure 1 A CMOS PA load matching network. [Color figure can beviewed in the online issue, which is available at www.interscience.wiley.com]

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Figure 2 The simulated power contour using conventional CMOS PAload matching network

Off-Chip L,C Matching Network

VGG

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RF_INN RF_INP

Thick Oxide Transistor Thin Oxide

Transistor

C1C2

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Figure 3 The schematic of cascode power amplifier with off-chip LCmatching. [Color figure can be viewed in the online issue, which isavailable at www.interscience.wiley.com]

900 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 50, No. 4, April 2008 DOI 10.1002/mop

values of passive component are determined by commercial avail-ability of chip passives.

The Figure 4 shows the obtained contour of measured RFoutput power for various L and C values. According to thepower contour, there may be more optimal impedance pointbeyond right-bottom area. However, unfortunately the chipcapacitors below 1 pF is unavailable commercially and lowestlimit of C becomes 1 pF. Nevertheless, the Figure 4 indicatesthat there is an optimal set of tuning values apparently. In actualdesign, so many tuning points are not required and if 4 or 5points are tried, the power-gradient and the plausible value areacan be found. And then one more try for 4 or 5 points aroundthe chosen value area will give us the nearly power-optimisticset of L and C values.

The optimal L and C values are found to be 8 nH and 1 pF,respectively. For these values the achieved output P1dB is 17.8 dBmat 2.4 GHz. The VDD power supply is 1.8 V and gate control biasVGG is 0.55 V. The measured power efficiency versus LC variablescan be also figured out in a contour as well as P1dB.

The Figure 5 shows the measured output power and corre-sponding power efficiency (PE) for chosen optimal L and C values.The measured maximum PE is 37%, which is considerably highamong those of previously reported class AB CMOS PA designs.The DC current consumption is 31 mA with small RF signal inputand increases up to 85 mA at power 1 dB compression power. Themeasured small signal gain 8 dB and input return loss S11 is below�10 dB. The fabricated test board of CMOS PA is shown inFigure 6 with microphotograph of PA chip. The chip size includingpads is 1 mm � 0.5 mm.

6. CONCLUSION

Contrary to PA design using III-V compound semiconductordevice, most of CMOS PA design are based on the simulationwith given MOS transistor models because load pull measure-

ment of CMOS devices has serious problems. However, design-ing the load matching network by simulation has also its lim-itation and errors due to unexpected parasitic such as packageand PCB board. Therefore, most of CMOS PA designers mayendeavor to optimize the external matching componentsthrough rigorous tuning. To overcome and clear the difficultiesof tuning procedure, a method based on the existence of con-tours of power and efficiency is proposed in this work. Thismethod can reduce the number of laborious trials and helpdesigners effectively find out the optimal values of tuningpassives. A tested CMOS PA shows that a useful contour of RFpower can be experimentally obtained and the optimal values ofL and C also can be found. The achieved P1dB and power

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Figure 4 The experimentally obtained RF power contour with L and C variables

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Figure 5 The measured output power and efficiency for optimal L and Cvalues. [Color figure can be viewed in the online issue, which is availableat www.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 50, No. 4, April 2008 901

efficiency of CMOS PA are 17.8 dBm at 2.4 GHz and 37%,respectively.

ACKNOWLEDGMENTS

The present research has been conducted by the Research Grant ofKwangwoon University in 2006. This research paper has been alsosupported by Nano IP/SoC Promotion Group of Seoul R&BDProgram in 2006.

REFERENCES

1. D. Su, et al, A 5 GHz CMOS transceiver for IEEE 802.11a wirelessLAN, ISSCC Dig Technical Pap, San Francisco, CA (2002), 92-93.

2. P. Reynaert and M. Steyaert, A 1.75 GHz GSM/EDGE polar modulatedCMOS RF power amplifier, ISSCC Dig Technical Pap, San Francisco,CA (2002), 312-313.

3. Y. Palaskas, et al, A 5-GHz 20-dBm power amplifier with digitallyassited AM-PM correction in a 90-nm CMOS process, IEEE J SolidState Circuits 41 (2006), 1757-1763.

4. T.C. Kuo and Bruce B. Lusignan, A 1.5W class-F RF power amplifierin 0.2 �m CMOS technology, ISSCC Dig Technical Pap, San Fran-cisco, CA (2001), 154-155.

© 2008 Wiley Periodicals, Inc.

MODIFIED MAXIMALLY FLATPARALLEL-COUPLED LINES FORBAND-PASS FILTER APPLICATIONSAND MINIATURIZATIONS

Ji-Chyun Liu,1 Bing-Hao Zeng,2 Jun-Mao Chang,1

Chi-Hsun Chien,1 Chung-Chi Chang,3 and Dau-Chyrh Chang2

1 Department of Electrical Engineering, Ching Yun University, Jung-Li,320, Taiwan; Corresponding author: jichyun@cyu.edu.tw2 Department of Communication Engineering, Yuan Ze University,Jung-Li, 320, Taiwan3 Department of Computer and Communication, China University ofTechnology, Hukou, Hsinchu, 303, Taiwan

Received 10 September 2007

ABSTRACT: The modified configurations of maximally flat parallel-coupled lines (MF-PCL) structure are introduced to improve the perfor-mance of the conventional MF-PCL resonator. To obtain a higher rejec-tion (�39 dB), symmetry response, wider band (BW about 32%), andless insertion loss (�0.4 dB) filters at central frequency 5.78 GHz, themodified MF-PCL resonators by using enhanced coupling techniquesare proposed herein. The size reduction of 50% is achieved. Results in-cluding surface current distributions and frequency responses are pre-sented and discussed. © 2008 Wiley Periodicals, Inc. Microwave OptTechnol Lett 50: 902–906, 2008; Published online in Wiley InterScience(www.interscience.wiley.com). DOI 10.1002/mop.23243

Key words: maximally flat; parallel coupled line (PCL); filter

1. INTRODUCTION

The attractive features of the microstrip PCL resonator are itscompact size, wide band, high rejection, and low insertion loss. Itis well known that PCL first introduced by Cohn [1]. This char-acter usually is applied to realize band-pass filters in microstripcircuits [2, 3]. The filters have the wide applications in satellitecommunication, mobile communication, wireless communication,and microwave system [4–17].

On the basis of the PCL resonator, various PLC configurationswere constructed in experiments [4]. This was an approach toimprove the upper stop-band rejection and response symmetry ofthe conventional PCL resonator. Meanwhile, the MF-PCL filtersusing maximally flat responses with wider band was reported forapplications [6, 7]. About 30% bandwidth was obtained, thus,those were applied for wide band-pass filter design. Recently,harmonic suppression techniques were proposed to improve theperformance of PCL resonator [8–13]. In addition, the miniatur-ized and compact PCL resonators were studied for applications[15, 16].

Improvements of MF-PCL filter with enhanced couple struc-ture for high performance band-pass filter design are presented inthis paper. The enhanced coupling techniques and the interactiveeffects are applied to modify the MF-PCL filter. Performance ofhigher rejection, symmetry response, wider bandwidth, less inser-tion loss, and miniaturizations are achieved and presented herein.For applications, results including surface current distributions andfrequency responses are presented and discussed.

2. FILTER CONFIGURATIONS AND BASIS

2.1. Typical PCL BasisTypical PCL resonator can be made with cascaded couple linesections [2, 3]. The PCL resonator composed of three coupled linesections is shown in Figure 1(a). The sections are numbered fromleft to right, with the load on the right. For a single section, when

PA chip

Load matching network

Figure 6 The photograph of fabricated CMOS PA with optimized loadmatching network. [Color figure can be viewed in the online issue, whichis available at www.interscience.wiley.com]

902 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 50, No. 4, April 2008 DOI 10.1002/mop