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PHYS 352

Analog-to-Digital Converters

Quantization Noise

original signal: sine wavethe digitized signal is an approximation of the originalit’s as though you added noise to the original to end up with your digitized outputlet’s calculate the signal-to-noise ratio from quantization

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consider a signal about zero with full-scale variation: 2 Vpn-bit ADC divides full scale into 2n steps:

linear approximation: the noise waveform is a triangular waveformtriangular waveform about zero has rms:

npV

=q2

2

Quantization Noise SNR

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2⋅

q

sinusoidal signal rms:

SNR (voltage):

SNR (power) = n*6.02 dB + 1.76 dB

( )22

22

np q=

V

( )n223

1.520log220log 1010 +n

Quantization Noise SNR cont’d

• the resolution of an analog-to-digital converter determines the signal-to-noise ratio (from the quantization noise is introduced)• after digitization, the resultant signal-to-noise ratio in the digital signal is approximately 6 dB*number of bits of the ADC

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use analog-to-digital converters (ADC's) for data acquisition and to digitize a signal for digital signal processingtwo key characteristics for ADC performance are:

resolutionsampling rate

physicaleffect transducer signal transmission

linesignal conditioning(amplifier, filter)

data acquisitionand display

n o i s e m a y e n t e r o r b e p r e s e n t

signalprocessing

Analog-to-Digital Converters

parallel encoder or flash ADCsubranging

digital ramptracking ADCsuccessive approximationsigma-deltasingle-slope integrationdual-slope integrationvoltage-to-frequency

the purpose of examining the inner workings is to guide your selection

Types of ADC's

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for n bits resolution, requires 2n-1 comparatorsconsumes power (many op-amps)fast! up to 20 GS/s!resolution limited to max 8-10 bitshigh-speed digital oscilloscopes use these (and other applications where ultra resolution is not required)fast pulse-shape digitization in physics experiments also use flash ADC'sprone to non-linearities

due to component tolerances

Flash ADC

Flash ADC cont’dimplementation of a priority encoder can be simple circuitry

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amplifysubtract off

also called pipelined ADCuses fewer comparators, draws less powere.g. 8 bit resolution requires 15+15 = 30 comparators as opposed to 255 in a true 8-bit flash ADCa little slower than a flash ADC (e.g. 100 MS/s)

but, the delay can be in the pipelinei.e. MSB for next sample while finishing LSB from previous

often extra overlapping bits used (e.g. 12 bits from 4+5+5) to correct “errors”

Subranging ADC

Subranging ADC Errorsduring digitization with the 2nd range, it requires the first range ADC and DAC components to generate exactly the correct amplitude signal to subtract off from the input

the residual signal must be perfectly in the range of the second ADC

by using overlapping bits, the extra resolution helps to correctfor errors introduced by interstage misalignment (or avoid them)

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Digital Rampsetting up for successive approximationDAC ramps up comparison voltage, used to see when input is crossedproblem: uneven time spacing – very bad!

Tracking ADCsimilar to the digital ramp except that instead of always counting up from zero, the counter also counts downcounter does not reset after digitization is completeimplemented in such a way that the counter tries to track the input value by counting up or downresult is a shorter time between digitization providedthe analog input does not change too rapidlysuffers from “bit bobble” in the LSB as the counter/DAC value has to cross the input to decide when to store the digital value

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Successive Approximation RegisterSAR used in place of a counterotherwise like digital ramptests n times, starting from MSB value down to LSB

when you require higher resolution and don't require high sampling ratecheaper and lower power consumption than subranginge.g. PC computer data acquisition cardrequire n settling times for the DAC for n-bit resolution

16 bits, 1 MS/s

Successive Approximation

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zeroing in on the final value and the LSB thru binary search

SAR in Action

integrates charge on a capacitorcounts the time it takes to charge and/or dischargebelow, illustrating the function of a single-slope integrating ADC

works just like a digital ramp, only without the DACsame problem as digital ramp – variable time of digitization

Integrating ADC

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counts the time to ramp charge up to the input level

Single-Slope Integration

simple in conceptbut, the circuit that integrates is separate from the counter (unlike digital ramp) – they will drift from each

sensitive to drifting R, drifting C, drifting comparator, drifting current source that charges the C, drifting clock…

so where is this used? when differential linearity is required but integral linearity is not so critical

very good channel width equality

dual-slope integration solves many problems

Single Slope – Not So Good

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charge the capacitor with the input voltagedischarge the capacitor with a reference voltage

insensitive to drifting C value

dual-slope integration (aka Wilkinson ADC) illustrated below

noise rejection!

t ∝ Vin

Dual-Slope Integration

good accuracy without extreme requirements on components; however, charge and discharge time means slower sampling ratescapacitor doesn't have to be particularly stable since the charge time and discharge time vary together if the capacitance driftsa comparator is used – beginning and ending voltages need to be fixed – but comparator op-amp drifts or scale errors cancel outused in single-shot applications & precision digital multimeters

handheld DMM’s have around 14-bit resolutiongood accuracy and stability for very low cost

Dual-Slope Integration Features

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additional benefit of integrating ADC is noise rejectionhigh frequency noise is rejected

because integration is like a low-pass filter

but also can choose the integration window of the ADC to be a multiple of the 60 Hz power-line period, for example

Integrating ADC Noise Rejection

used in audio and high-resolution data acquisitioncapable of very high resolution (e.g. 24 bits)however, slower sampling rates (up to 100 kS/s is common)it's oversampled (e.g. 100 kS/s actually samples at 128× or 12.8 MS/s)

1-bit ADC what is that?digital filter

Sigma-Delta ADC

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will require learning about digital filters and digital signal processing, which we will get to next in lecturesfor now, we will take a glimpse at oversampling

FFT of the digital output FFT of the digital output

Understanding Oversampling

1-bit ADC has 7.78 dB SNR (signal-to-noise ratio)but, the noise power is spread over k times the frequency rangeeach factor 4n in oversampling gains n*6 dB

64× oversampling 1-bit, gains 3 bits ≃ 4-bit resolution

Apply Digital Filter to Oversampled Data

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you can also understand how oversampling improves signal-to-noise by just considering statisticsif you measure a quantity N times, your uncertainty (standard deviation of the mean) goes asexample

0.0-2.5 V input corresponds to digital output 02.5-5.0 V input corresponds to digital output 1an analog input signal of 2.6 V → generates a digital output 1imagine deliberately adding Gaussian noise to the analog signal of say ±0.2 Vnow, perform 16 digitizations of 2.6 ± 0.2 V; you get 1’s and 0’stake the average value of the 1’s and 0’s and it will be something close to 0.5 (slightly more 1’s than 0’s)oversampling enabled you to determine an intermediate value –you’ve increased your resolution by oversampling

Alternative View: Oversampling

N/1

step #1 for a Σ-Δ is: oversamplingstep #2 for a Σ-Δ is: noise shaping

Σ-Δ designed to force quantization noise power to higher frequencies

improves performance of oversamplingthe gain can be 9 dB for every 2× oversampling (rather than 6 dB for every 4×)e.g. 128× oversampling gives 9*7 = 63 dB, adding about 10 bits equivalent resolution

Σ-Δ Noise Shaping

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the analog part is a 1st order sigma-delta modulator that achieves the desired quantization noise shaping

a flip-flop flips this back and forth based on 1-bit data stream

Sigma-Delta Modulator

how it works!

Σ-ΔADC

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Σ-Δ Tutorial Applet

http://designtools.analog.com/dt/sdtutorial/sdtutorial.html

recap: steps of Σ-Δ areoversamplingnoise shapingdigital filtersample decimation

the digital filter and decimation are often put togetherexample of decimator

feed the decimator sixteen 1-bit values (0’s and 1’s)it simply counts how many 1’s there were out of the 16outputs one 4-bit digital value to represent how many 1’s

if you have a sampling rate of fs and want to reduce to fs/M, where M is an integer, the decimator does that without loss of information provided fs/M is above the Nyquist criterion

Sample Decimator

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uses the same capacitor (or integrator) for the signal and the reference, so the design is forgiving of capacitor stability and accuracyfewer demands on the comparator (1-bit compare to zero!)inherently linear (just one comparator)

you trade reduced accuracy requirements in the analog part of the design for increased complexity on the digital side; but, these days, digital is cheap and easyin summary, you can get higher accuracy and precision with lower cost components

Features of Sigma-Delta

higher voltage gives rise to higher current charging capacitorwhen the capacitor charge ramps up to Vcomp, it generates a pulse that also discharges the capacitorrepeat...pulse frequency is proportional to voltage

Voltage-to-Frequency

NOT GOING TO COVER IN

THIS COURSE

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count the generated pulse train to get digital output value

V/F ADC Pulse Illustration

NOT GOING TO COVER IN

THIS COURSE

Summary: ADC’sthere are a few other (not so common) ADC designs out thereknowing the main types described in this lecture and understanding their basic inner workings helps you know their advantages/disadvantages in terms of

sampling rateresolutionsensitivity to component quality (which impacts stability and linearity)

reference: http://www.allaboutcircuits.com/vol_4/chpt_13/index.html