IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 6, JUNE 2013 729

Origins of Effective Work Function Roll-OffBehavior for High-κ Last Replacement

Metal Gate StacksTakashi Ando, Senior Member, IEEE, Eduard A. Cartier, John Bruley, Kisik Choi, Senior Member, IEEE,

and Vijay Narayanan, Senior Member, IEEE

Abstract— Origins of effective work function (EWF) roll-off behavior accompanied by equivalent oxide thickness (EOT)scaling for high-κ last replacement metal gate (RMG) stacksare investigated using a low-temperature interfacial layer (IL)scavenging technique. The EWF-EOT roll-off is driven by a highwork function metal and the trend is linear and reversible bymeans of IL scavenging and regrowth reactions. These findingsare consistent with the oxygen vacancy model, indicating that thesame mechanism that plagued gate-first devices emerges as theIL thickness is scaled <4 Å (EOT 8 Å) for RMG stacks.

Index Terms— Effective work function, gate-last, high-κ ,replacement metal gate, scavenging.

I. INTRODUCTION

CONTINUED CMOS device scaling requires a high-κgate dielectric with a subnanometer equivalent oxide

thickness (EOT). Scaling of a low-permittivity interfacial layer(IL) between a Si substrate and a HfO2 layer via scavengingreaction is gaining momentum in meeting this requirement[1]. Most IL scavenging approaches require relatively high-temperature chemical reactions, limiting their application togate-first process [2]–[4]. Therefore, EOT scalability for thehigh-κ last replacement metal gate (HKL RMG) process [5]has yet to be investigated. In addition, it is reported thatthe effective work function (EWF) roll-off behavior emergesfor RMG process at EOT <9 Å [6], [7]. Similar EWFroll-off behaviors are initially reported for gate-first processat a much thicker EOT regime (∼30 Å), motivating manypeople to move to gate-last process to realize low thresholdvoltage p-type field-effect transistors (pFETs). The EWF roll-off behavior for gate-first process is attributed to oxygenvacancy generation in a HfO2 layer [8] or a SiO2 IL [9].However, oxygen vacancy generation typically requires a high-temperature process (>600 °C) and the mechanism underlyingthe EWF roll-off for RMG process is not well understood. Inthis letter, we establish an IL scavenging technique compatiblewith a low-temperature process and develop insights into theorigin of the EWF roll-off behavior for the HKL RMG process.

Manuscript received April 4, 2013; accepted April 16, 2013. Date ofpublication May 13, 2013; date of current version May 20, 2013. This workwas supported by the Research Alliance Teams at various IBM Researchand Development Facilities. The review of this letter was arranged by EditorK.-S. Chang-Liao.

T. Ando, E. A. Cartier, J. Bruley, and V. Narayanan are with theT. J. Watson Research Center, IBM, Yorktown Heights, NY 10598 USA(e-mail: andot@us.ibm.com).

K. Choi is with Globalfoundries, Yorktown Heights, NY 10598 USA.Color versions of one or more of the figures in this letter are available

online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2013.2259136

Fig. 1. Process flow and schematics showing change in IL thickness at keysteps. Cross-sectional TEM images are taken at steps (1)–(3).

II. EXPERIMENTAL

We fabricate 10 × 10 μm2 MOS capacitors on n-typeSi substrates with a doping concentration (Nsub) of5 × 1015 cm−3 using a process flow simulating HKLRMG process as shown in Fig. 1. After HfO2 deposi-tion, an optional postdeposition anneal (PDA) is performedat a temperature higher than typical conditions for HKLRMG (500 °C–700 °C) [10]. Then, a sacrificial TiN gate(Sac-TiN) doped with scavenging metal is deposited. Thescavenging metal is chosen such that the remote IL scavengingreaction happens during the subsequent Poly-Si deposition at600 °C [11]. The final IL thickness is continuously varied bychanging the amount of metal doping. Next, both the Poly-Si layer and the Sac-TiN are removed by wet etching. For theaggressive EOT scaling experiment, optional La2O3 cap layersare deposited, followed by deposition of the TiN/TiAl stackas n-type FET (nFET) work function (nWF) metal. For theEWF roll-off experiment, optional low oxygen partial pressure(PO2 < 1 mTorr) anneals [details in Fig. 4(b)] are performedon the exposed HfO2, followed by deposition of TiN as pFETwork function (pWF) metal. Then, the trench is filled withAl and 400 °C furnace anneal (N2, 50 m) is performed tosimulate the thermal budget of CMOS integration. Cross-sectional transmission electron microscopy (TEM) is carriedout at various steps in the process flow to trace the changein the IL thickness. The EOT values are extracted fromcapacitance–voltage (CV) measurement using Hauser’s fittingmodel [12]. The CV measurements are performed by anHP4284A precision LCR meter at 300 kHz. The EWF valuesare calculated from the Vfb, Nsub, and EOT. Therefore, allgate stack related factors besides the metal work function,such as fixed charges and interface dipoles, are included inthe estimation of EWF.

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730 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 6, JUNE 2013

Fig. 2. Cross-sectional TEM images taken after (a) sac-TiN deposition,(b) sacrificial Si deposition and removal, and (c) final 400 °C furnace anneal,which correspond to steps (1)–(3) in Fig. 1, respectively.

Fig. 3. (a) EOT–Jg characteristics for nFET stacks with and without La2O3cap. The Jg is measured at Vfb+1 V. The best data reported for gate-first[11] is shown for comparison. (b) CV curve corresponding to gate stack withthinnest IL thickness with La2O3 cap (EOT 4.2 Å).

III. RESULTS AND DISCUSSION

The TEM images taken at steps (1)–(3) in Fig. 1 are shownin Fig. 2(a)–(c), respectively. The chronological change inthe IL thickness indicates that remote IL scavenging reactionhappened at the Poly-Si deposition [Fig. 2(a) and (b)] and theIL thickness is maintained thin until the end of the processflow [Fig. 2(c)]. Fig. 3(a) shows EOT–Jg characteristics for thenFET stacks. The Jg is measured at Vfb + 1 V. The multipledata points are obtained by changing the IL thickness viaremote IL scavenging with a fixed HfO2 thickness. The trendswith and without the La2O3 cap are compared. The slope forthe IL scavenging is close to that of SiO2/Poly-Si (i.e., 10×increase in Jg/2 Å scaling, shown in broken lines) indicatingthat it follows the ideal SiO2 IL scaling trend and no extrinsicdegradation is involved. In addition, the La2O3 cap providesadditional 10× Jg reduction with little EOT penalty. Middleenergy ion scattering shows that an initial surface layer ofLa2O3 diffuses through a HfO2 layer at elevated temperatures(> 800 °C) [13]. As post-La2O3 thermal budget is limited to400 °C in this letter, such penetration does not occur andno dipole-induced Vfb shift is observed, which makes thiscapping technique applicable to pFET as well. The thinnest ILthickness with the La2O3 cap achieved EOT 4.2 Å and Jg 3.5A/cm2, showing leakage reduction of more than five ordersof magnitude compared with the conventional SiO2/Poly-Sistack. The corresponding CV curve is shown in Fig. 3(b).This is comparable with the best value reported for gate-firstprocess [11].

Fig. 4. (a) EWF-EOT trends for IL/HfO2 stacks with nWF metal (square)and pWF metal (circle). The multiple data points are obtained by continuouslychanging the IL thickness via remote IL scavenging. (b) EWF-EOT trendsfor pWF metal with IL scavenging (open square), subsequent regrowth bythe low PO2 RTAs (numbered square), and high-κ PDA (open circle). Thecorresponding temperatures and times for the low PO2 RTAs are summarizedin the table.

We use the Sac-TiN technique to explore the origin ofthe EWF roll-off behavior. Fig. 4(a) compares the EWF-EOTtrends for the nWF and pWF metals. The multiple data pointsare obtained by continuously changing the IL thickness. ThenWF metal provides a completely flat EWF-EOT trend downto 6 Å, indicating that our IL scavenging process per se didnot create fixed charges or dipoles within the gate stack. Onthe other hand, the pWF metal shows a flat trend down toEOT 8 Å and then exhibits a linear tradeoff trend towardthe midgap with further scaling. This sharp contrast stronglysuggests that the metal work function is the driving force ofthe phenomenon. Akasaka et al. proposed the oxygen vacancy(Vo)-induced p-metal pinning model with the energy differ-ence between the metal work function and the Vo level beingthe driving force [14]. Our data for HKL RMG with scaled ILsis analogous to Akasaka’s model for high-temperature process.Next, we perform low PO2 rapid thermal anneals (RTAs) afterthe IL scavenging. Fig. 4(b) shows the impact of IL scavenging(open square) and subsequent regrowth by the low PO2 RTAs(numbered square) on the EWF-EOT trend for the pWF metal.The corresponding temperatures and times for the low PO2RTAs are summarized in the table in Fig. 4(b). The EWF-EOT tradeoff at EOT < 8 Å is highly linear and reversibleby means of IL scavenging and subsequent regrowth from thelow PO2 RTAs. This trend indicates that the IL thickness is thedetermining factor of the EWF of pFET. Guha et al. predicteda linear change in the EWF as a function of the IL thicknesswhen the system reaches a steady state of oxygen transfer fromthe HfO2 to the Si substrate, as expressed by the followingequation [15]:

�φ = − 2el2HfO2

at�Bεrε0lSiO2 + C (1)

ANDO et al.: ORIGINS OF EFFECTIVE WORK FUNCTION ROLL-OFF BEHAVIOR 731

where �φ is the EWF change, e is the electron charge, lHfO2is the HfO2 thickness, lSiO2 is the SiO2 thickness, a is inthe order of a lattice constant, t is the time for SiO2 growth,� is a constant for the growth rate of SiO2 via the oxygenexchange across the SiO2/HfO2 interface, B is a constant forthe annihilation rate of Vo in HfO2, εr is the dielectric constantof SiO2, ε0 is the vacuum permittivity, and C is a constant.Our data suggest that the steady state is reached at 400 °C forRMG process when the IL thickness scales <4 Å (EOT 8 Å).With our direct tunneling current analysis of SiO2/HfO2 dual-layer stacks, it is suggested that the band offsets for theSiO2 and HfO2 layers are reduced in the submonolayer ILregime, which may be related to the existence of a suboxidetransition region at the Si/SiO2 interface (∼3 Å) [16]. Thedegradation in IL quality may facilitate transfer of oxygenatoms from the HfO2 layer to the Si substrate, resulting inthe unfavorable EWF shift for pFET even with RMG process.Generally, the Vo generation is attributed to the high-thermalbudget of gate-first process [8], [14]. Our finding suggeststhat the same mechanism occurs at moderate temperatures(∼400 °C) when the IL thickness is scaled below the criticalthickness (4 Å). Fig. 4(b) also compares the EWF-EOT trendswith and without the high-κ PDA (open circle and opensquare, respectively). The EWF-EOT slope at EOT <8 Åcan be drastically improved (300–100 mV/Å) by employingthe optimized high-κ PDA. This change is attributable tosuppressed oxygen transfer [change in � and/or B in (1)]via improvement in film quality. In addition, the EWF of theflat regime (EOT > 9 Å) is boosted by 50–100 mV withthe high-κ PDA, which may be because of reduction of filmimpurities. The high-κ PDA also moves the threshold EOTvalue where the EWF starts to roll off. More research isneeded to understand this trend. The EWF-EOT slope with thehigh-κ PDA in this letter is in a good agreement with theliterature [6], [7]. Thus, high-κ PDA is a crucial knob tomitigate the fundamental EWF-EOT tradeoff for pFET andto attain further EOT scaling with HKL RMG process.

IV. CONCLUSION

We established an IL scavenging technique compatible witha low-temperature process and achieved EOT 4.2 Å with HKLRMG process. We found that the EWF-EOT roll-off for RMGprocess was driven by metal work function and highly linearand reversible by means of IL scavenging and regrowth reac-tions. These findings were consistent with the oxygen vacancymodel, indicated that the same mechanism that plaguedgate-first devices emerged as we scaled the IL thickness<4 Å (EOT 8 Å) for RMG process. We demonstrated thathigh-κ PDA was a crucial knob to mitigate this fundamentaltradeoff and to attain further EOT scaling for RMG process.

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