MIC511

Analysis and Design of Analog Integrated Circuits

Lecture 11

Examples

Michael H. Perrott

Masdar Institute of Science and Technology

March 4, 2012

Copyright c© 2012 by Michael H. Perrott

All rights reserved

Example Analysis Circuit

M6

M1 M2

M5

Ibias1

Vin

M3 M4

50 Ω50 Ω

VoutM13

M7

M14

M9

M8

M11

M10

M12

M15

M16

M17

M18

M19

M20

M21

M23

M22

M24

Q1

Cbig

50 Ω

(external)

• Assumptions

1. Intrinsic gain of each device � 1

gmro � 1 =⇒ 1/gm � ro

2. Intrinsic gain of devices similar in value

3. Output resistances of devices similar in value

ro1 ≈ ro2

• Note:

– Assumption 1 is reasonable in practice

– Assumptions 2 and 3 are invalid in practice

∗ Used here only for pedagogical reasons

Replace Current Sources

M6

M1 M2

M5

Ibias1

Vin

M3 M4

50 Ω50 Ω

VoutM13

M7

M14

M9

M8

M11

M10

M12

M15

M16

M17

M18

M19

M20

M21

M23

M22

M24

Q1

Cbig50 Ω(external)

currentsource

current mirrorbias

current mirrorbias

currentsource

currentsource

currentsource

currentsource

currentsource

currentsource

currentsource

cascodebias

M1 M2

M5

Ibias1

Vin

M3 M4

50 Ω50 Ω

Vout

M9

M8

M15

M16

M21

M23

Q1

Cbig50 Ω(external)

current mirrorbias

current mirrorbias

cascodebias

M1

ro6

ro22ro7

ro24

(gm18ro18)ro17

(gm13ro13)ro12

(gm10ro10)ro11 (gm19ro19)ro20

Remove Non-Signal-Path Biasing Circuitry

M1 M2

Vin

M4

50 Ω50 Ω

Vout

M9

M8

M23

Q1

50 Ω

current mirrorbias

current mirrorbias

cascodebias

M1

ro6

ro22ro7

ro24

(gm18ro18)ro17

(gm13ro13)ro12

(gm10ro10)ro11 (gm19ro19)ro20

gm211

gm51

assumecap is short

gm151

gm31

M1 M2

Vin

M4

50 Ω

50 Ω

Vout

M9

M8

M23

Q1

50 Ω

M1

ro6

ro22ro7

ro24

(gm13ro13)ro12

(gm10ro10)ro11

assumecap is short

gm31

vinput

Stage 1 Stage 2 Stage 3

Bipolar Modeling is similar to CMOS

RthgAvvgvg

isRths

Rthdisα

g

s

d

General Thevenin Model

Av = 1α = 1

gmb << gm

Approximation Assumption

Rd << Rthd

RS

RG

RD

Rthd

Rths

Rthg

ID

Rthd= ro (1+gmRS)

Rthg= infinite

Rths=

1 + RD /rogm

gmb << gm

gmb << gm

Thevenin Resistances

Approximation Assumption

gm = μnCox(W/L)(VGS - VTH)

= 2μnCox(W/L)ID

gmb << gm

λID1ro =

Key Small-Signal Parameters

ro = IcVA

, VA

Vt 25 mV at room temp~~

100 to 200 V~~

, βo 100 to 200~~

IcVt

,Vt =kTqgm =

βogm

rπ =

Key Small-Signal Parameters

RE

RB

RC

Rthc

IC

Rthe

Rthb

Rthc= ro (1+gm(rπ||RE))

Rthb= rπ + βoRE

Rthe= 1/gm + RB/βo

RC+RE << ro

RB << rπ

RC << βoro

Thevenin Resistances

Approximation Assumption

RthbAvvbvb

ieRthe

Rthcieα

b

e

c

General Thevenin Model

Av = 1α = 1

Approximation Assumption

RC+RE << βoro

RC+RE << ro, RB << rπ

MOSFET BIPOLAR

, gmro >> 1

Compute 2-port for Stage 3

50 Ω

Vout

M23

Q25

ro22

ro24

Stage 3

Vb

Vb

vgvg

gm23

1

vb25vb25 vout

gm25

1βo gm25

1rπ + βo(50||ro24)

50||ro24

gm25

1

rπ + βo50

rπ + βo50 50

50

M23

Q25

Vb

vg

gm23

1vout

gm25

1(rπ + βo50)||ro22

50(rπ + βo50)||ro22

vg

Vb

vg voutgm25

1

50

(gm10ro10)ro11

outputresistanceof Stage 2

( ||ro22)gm23

1

ro22

gm23

1

(rπ + βo50)||ro22

(rπ + βo50)||ro22

vg

Compute 2-port for Stage 2

M9

M8

ro7

(gm13ro13)ro12

(gm10ro10)ro11

Stage 2

Vb

Va

αis

is

ro7Va

1 + RD /ro8

gm8(gm9(ro9||RA))

(ro7||ro4||ro2)(gm8ro8)(gm9(ro9||RA))

RA

ro7/3(gm8ro8)(gm9ro9)

RD

1 + (gm10ro10)ro11 /ro8

gm8(gm9ro9)

ro11 /ro8gm8

1gm8

1gm8 ro7/3(gm8ro8)(gm9ro9)

(gm10ro10)ro11

Vb

RD

ro2||ro4

outputresistanceof Stage 1

inputresistanceof Stage 3

is

is

1gm8

(gm10ro10)ro11

Va Vb

is =

ia

1gm8

||ro71

gm8

ro71

gm8+ ro7

ia ia

(gm10ro10)ro11 /ro8

gm8(gm9ro9)

is

Compute 2-port for Stage 1 (Step 1)

M1 M2

Vin

M4

50 Ω

50 Ω

M1

ro6

gm31

vinput

Stage 1

Va

inputresistanceof Stage 2

1gm8

M1 M2

M4

25 ΩM1

ro6

gm31

inputresistanceof Stage 2

2vinput

ro4

ro2

gm11 ||ro6 gm1

1

(1+gm2 )gm11

2ro21

gm8

gm21 ||ro6 gm2

1

ro1(1+gm1 )gm21

2ro1

Vin

Calculate Thevenin resistances

infinite

Compute 2-port for Stage 1 (Step 2)

isc

M2

M4

25 ΩM1

ro6

gm31

2vinput

ro4

gm21

gm3= gm4 is1

1i2

vg1vg1

is1

αis1gm11

2ro1

Vin

is1

Vin

gm11

gm21

Vingm1

2

is1 =is1

is1

is1

isc 2is1 Vin gm1

M1 M2

M4

25 ΩM1

ro6

gm31

gm11

2ro2

ro1(1+gm1 )gm21

2ro1

Vin

it

vti1=

i1i1

i1

i1

itvtro4

+2i1vtro4

+2vt

2ro2=

vt

it= ro2||ro4

Calculate short circuit current at output

Calculate output resistance

vtro4

gm4vg4vg4 ro4

vt2ro2

Compute 2-port for Stage 1 (Final Step)

M1 M2

Vin

M4

50 Ω

50 Ω

M1

ro6

gm31

vinput

Stage 1

Va

inputresistanceof Stage 2

1gm8

25 Ω

2vinput

Vin

gm1vg1vg1 ro2||ro4

Va

Overall Cascade of 2-ports for Amplifier

25 Ω

2vinput

Vin

gm1vg1vg1 ro2||ro4

Va

vg voutgm25

1

50

ib

ib

1gm8

(gm10ro10)ro11

Vb

Stage 1

Stage 2

Stage 3

gm23

1

(rπ + βo50)||ro22

(rπ + βo50)||ro22

vg

• What is the overall input/output resistance of the amp?

• What is the overall gain?

• Which stage contributes the most gain?

• What is the function of each stage?