Logic Circuits II - Department of Physics ::...

Physics116B, 2/6/06

D. Pellett

Logic Circuits II

Outline

• Emitter-Coupled Logic (ECL) example from Bobrow, Ch. 7

• Commercial ECL specifications and some applications

• Short pulses and transmission lines - quick overview

• Using ECL to drive transmission lines

• ECL and NIM logic

• Logic family comparisons

• Interconnections, “dos and don’ts”

• More recent developments

Emitter Coupled Logic (ECL)

• ECL circuits are fast (1 ns delays typical) because they avoid saturation

• Can drive low impedance loads such as 50 Ω coaxial cables

• May have complimentary outputs to drive pairs of lines differentially (strip lines, twisted pairs, etc.)

• Because BJTs remain in active region, power dissipation significantly higher than TTL, low packing density on chip

• Circuit based on differential amplifier with non-inverting input connected to reference voltage, one BJT cut off and the other in active region

• Supply voltage and logic levels typically <0.

• Emitter follower outputs

• May have “open emitter” output

Basic ECL Inverter Concept

• Design so Q1 active, Q2 off when Vin high,

• opposite w/ Vin low

• Determine logic levels next

Differential Amplifier

InvertingInput

Non-InvertingInput

NOTE: Circuit based on Fig. 7.43 in BobrowCommercial circuits differ in Vref, VEE and BJT VBE(active) so actual ECL levels are different.

(Vref)

(VEE)

-1.7 V

≈ 0 V-0.7 V

Low

ActiveOff

< -1.2 V

• Assume Vin low so Q1 off and Q2 in active region

• VBE2 = 0.7 V so VE = -1.7 V

• Since Q1 off, VC1 ≈ 0 V, so V0 = -0.7 V (high logic state). Note Q3 is in active region with VBE3 = 0.7 V and VC = 0 V: VCE3 = 0.7 V (> 0.2 V)

• Voltage drop across R1 is negligible: IE3 = (5-0.7)V/1.2 kΩ = 3.6 mA → IB3 ≈ 36 µA, IB3 R1 = 10 mV.

Find Output V in High State

(VB1 < VE + 0.5 V)

High

Find Low State Output Voltage

-0.7 VHigh

Active Off

-1.4 V

Low

• Assume Vin high and Q1 in active region

• VBE1 = 0.7 V so VE = -1.4 V. → VBE2 = 0.4 V so Q2 off

• IE = IE1 = (-1.4 -(-5))V/1.2 kΩ = 3.0 mA

• VC1 = VB3 ≈ -(3.0 mA)(275 Ω) = -0.82 V → VO = -1.52 V (low state output voltage, < -1.2 so low OK at input)

-0.82 V-1.52 V

Make into OR/NOR

• Adding Q0 in parallel with Q1 produces a NOR function at Q3 emitter.

• Adding an emitter follower connected to collector of Q2 produces the complement of the function, an OR.

Actual MECL 10K ECL OR/NOR

• BJT VBE = 0.8 - 0.9 V for active region, VBB = -1.35 V, VEE = -5.2 V

• Logic levels are -0.9 V and -1.75 V (nominal)

• Note open emitter outputs

Fourth EditionAuthor: William R. Blood, Jr.

HB205/DRev. 1A, May–1988

MECL System

Design Handbook

! SCILLC, 2000

Previous Edition !1980, 1988

“All Right Reserved”

Date of this Printing: Aug–2000

MC10H102

http://onsemi.com2

MAXIMUM RATINGS

Symbol Characteristic Rating Unit

VEE Power Supply (VCC = 0) –8.0 to 0 Vdc

VI Input Voltage (VCC = 0) 0 to VEE Vdc

Iout Output Current– Continuous

– Surge

50

100

mA

TA Operating Temperature Range 0 to +75 °C

Tstg Storage Temperature Range – Plastic

– Ceramic

–55 to +150

–55 to +165

°C

°C

ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)

0° 25° 75°

Symbol Characteristic Min Max Min Max Min Max Unit

IE Power Supply Current – 29 – 26 – 29 mA

IinH Input Current High – 425 – 265 – 265 µA

IinL Input Current Low 0.5 – 0.5 – 0.3 – µA

VOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc

VOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc

VIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc

VIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc

AC PARAMETERS

tpd Propagation Delay 0.4 1.25 0.4 1.25 0.4 1.4 ns

tr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

tf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been

established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is

maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.

From MECL Handbook, 4th ed.

Quad 2-Input NOR

! Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 61 Publication Order Number:

MC10H102/D

The MC10H102 is a quad 2–input NOR gate. The MC10H102

provides one gate with OR/NOR outputs. This MECL 10H part is a

functional/pinout duplication of the standard MECL 10K family part,

with 100% improvement in propagation delay, and no increases in

power– supply current.

• Propagation Delay, 1.0 ns Typical

• Power Dissipation 25 mW/Gate (same as MECL 10K)

• Improved Noise Margin 150 mV (Over Operating Voltage and

Temperature Range)

• Voltage Compensated

• MECL 10K–Compatible

LOGIC DIAGRAM

DIP

PIN ASSIGNMENT

VCC1

AOUT

BOUT

AIN

AIN

BIN

BIN

VEE

VCC2

DOUT

COUT

DIN

DIN

CIN

CIN

DOUT

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8

14

13

12

11

10

37

6

25

4

159

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion Tables on page 18

of the ON Semiconductor MECL Data Book (DL122/D).

http://onsemi.com

Device Package Shipping

ORDERING INFORMATION

MC10H102L CDIP–16 25 Units/Rail

MC10H102P PDIP–16 25 Units/Rail

MC10H102FN PLCC–20 46 Units/Rail

MARKING

DIAGRAMS

1

16

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

CDIP–16

L SUFFIX

CASE 620

MC10H102LAWLYYWW

PDIP–16

P SUFFIX

CASE 648

PLCC–20

FN SUFFIX

CASE 775

10H102

AWLYYWW

1

1

16

MC10H102PAWLYYWW



MC10H102/D









Temperature Range)



LOGIC DIAGRAM

DIP

PIN ASSIGNMENT

VCC1

AOUT

BOUT

AIN

AIN

BIN

BIN

VEE

VCC2

DOUT

COUT

DIN

DIN

CIN

CIN

DOUT

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8


14

13

12

11

10

37

6

25

4

159




http://onsemi.com






MARKING

DIAGRAMS

1

16


WL = Wafer Lot

YY = Year

WW = Work Week

CDIP–16

L SUFFIX

CASE 620

MC10H102LAWLYYWW

PDIP–16

P SUFFIX

CASE 648

PLCC–20

FN SUFFIX

CASE 775

10H102

AWLYYWW

1

1

16

MC10H102PAWLYYWW

MECL NOR Specifications



MC10H102/D









Temperature Range)



LOGIC DIAGRAM

DIP

PIN ASSIGNMENT

VCC1

AOUT

BOUT

AIN

AIN

BIN

BIN

VEE

VCC2

DOUT

COUT

DIN

DIN

CIN

CIN

DOUT

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8


14

13

12

11

10

37

6

25

4

159




http://onsemi.com






MARKING

DIAGRAMS

1

16


WL = Wafer Lot

YY = Year

WW = Work Week

CDIP–16

L SUFFIX

CASE 620

MC10H102LAWLYYWW

PDIP–16

P SUFFIX

CASE 648

PLCC–20

FN SUFFIX

CASE 775

10H102

AWLYYWW

1

1

16

MC10H102PAWLYYWW

MC10H102

http://onsemi.com2

MAXIMUM RATINGS





– Surge

50

100

mA



– Ceramic

–55 to +150

–55 to +165

°C

°C


0° 25° 75°









AC PARAMETERS


tr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

tf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns




Pulses and Transmission Lines

Transmission Line Circuit Model(Ideal, lossless)

Typical Characteristic Impedance Values Other Transmission Line Advantages

Lots of Useful Information on Fast Pulse Techniques in MECL Handbook



MECL System

Design Handbook

! SCILLC, 2000




MC10H102

http://onsemi.com2

MAXIMUM RATINGS





– Surge

50

100

mA



– Ceramic

–55 to +150

–55 to +165

°C

°C


0° 25° 75°









AC PARAMETERS


tr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

tf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns





• Web link to download MECL Handbook (pdf):

http://www.onsemi.com/pub/Collateral/HB205-D.PDF

Pulse Response on “Open Wire”



MECL System

Design Handbook

! SCILLC, 2000




MC10H102

http://onsemi.com2

MAXIMUM RATINGS





– Surge

50

100

mA



– Ceramic

–55 to +150

–55 to +165

°C

°C


0° 25° 75°









AC PARAMETERS


tr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

tf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns





ECL Driving 50 Ω Coaxial Cable



MECL System

Design Handbook

! SCILLC, 2000




MC10H102

http://onsemi.com2

MAXIMUM RATINGS





– Surge

50

100

mA



– Ceramic

–55 to +150

–55 to +165

°C

°C


0° 25° 75°









AC PARAMETERS


tr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

tf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns




From MECL Handbook, 4th ed. Much Better!

ECL Differential Line Driver and Receiver



MECL System

Design Handbook

! SCILLC, 2000




MC10H102

http://onsemi.com2

MAXIMUM RATINGS





– Surge

50

100

mA



– Ceramic

–55 to +150

–55 to +165

°C

°C


0° 25° 75°









AC PARAMETERS


tr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 ns

tf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns





NIM Electronics

• ECL can be made to interoperate directly with NIM logic levels with suitable choice of offset ECL power supply voltages

AN INTRODUCTION TO NIM (From Fermilab web site)

The NIM standard (DOE/ER-0457), originally an acronym for Nuclear Instrumentation Methods, was established in 1964 for the nuclear and high energy physics communities. The goal of NIM was to promote a system that allows for interchangeability of modules. Even today experimenters use NIM modules to assemble a system which meets the specific requirements of their experiment.

Standard NIM modules are required to have a height of 8.75", and must have a width which is a multiple of 1.35". Modules with a width of 1.35" are referred to as single width modules and modules with a width of 2.7" are double width modules, etc. The NIM crate, or NIM bin, is designed for mounting in EIA 19" racks, providing slots for 12 single-width modules. The power supply, which is in general, detachable from the NIM bin, is required to deliver voltages of +6 V, -6 V, +12 V, -12 V, +24 V, and -24 V. The standard NIM power connectors and pinouts are shown the Bin Connector Diagram, Module Connector Diagram and Pin/Function Table. The LeCroy NIM bin and power supply, Model 1403, adhere to all NIM specifications.

The NIM standard also specifies three sets of logic levels. In fast-negative logic, usually referred to as NIM logic, logic levels are defined by current ranges. Since the standard also requires 50 W input/out impedances, these current ranges correspond to voltages of 0 V and -0.8 V for logic 0 and 1 respectively. Fast-negative logic circuitry can provide NIM signal with rise times of order 1 nsec. Slow-positive logic, is rarely used in fast-pulse electronics due to the slow rise times involved, and is not implemented in LeCroy modules. Specifications for ECL (emitter-coupled logic) voltage levels and interconnections have been added to the NIM standard at the request of LeCroy. The logic levels, header sizes, cable terminations, etc., is specified in the standard. The TTL logic system may be used in NIM modules, but is not specified in the NIM standard. LeCroy provides the Model 688AL and the Model 4616 for NIM/TTL and ECL/NIM/ECL level translations. LeCroy also provides the Model 4501A adaptor, which allows a NIM modules to be used in a CAMAC crate.

(From http://www-esd.fnal.gov/esd/catalog/intro/intronim.htm)

• Collecting data from high energy proton-antiproton collisions. But not all chips are microchips in this experiment (see foreground).

• Note NIM electronics bin in rack near back corner

Collider Detector at Fermilab (CDF) Control Room – Lots of fast pulses!

Some CDF Control Room Electronics

• NIM Bin

• Some of the other bins are CAMAC bins

• Much custom electronics in use elsewhere in experiment, some “standard” (e.g. VME), some not

• Similar equipment is also in use in the Physics122 lab next door in Roessler

Logic Family Comparisons

• See Tables 12.5 and 12.6 in Bobrow, Tables 9.1 and 9.2 in Horowitz and Hill

• Important families: TTL, STTL, LSTTL, CMOS, HC, HCT, ECL

• Important parameters: pulse delay, power per gate, logic level ranges, supply voltages, fanout

• Incompatibilities of CMOS and HC with TTL high output

• See also later slides from the Texas Instruments Logic Selection Guide (2005)

Some Precautions

• TTL –

• Inputs normally float “high” but if you desire high state connect to VCC for noise immunity

• Bypass VCC to ground frequently near or at the chips with 0.01 µF – 0.1 µF capacitors to prevent glitches due to switching spikes on the supply lines.

• CMOS –

• Note that TTL outputs are not high enough for normal CMOS inputs in high state – can remedy with pull-up resistor to VCC.

• Connect all CMOS inputs to definite logic levels. Otherwise input can float to a voltage where pMOS and nMOS FETs are conducting leading to short between VSS and VDD.

Recent Logic Families

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