DIGITAL LOGIC DESIGN NO. 1 (Boolean Algebra & Logic Gates) From APCOMS

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Boolean Algebra & Logic Gates
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Transcript of DIGITAL LOGIC DESIGN NO. 1 (Boolean Algebra & Logic Gates) From APCOMS

Boolean Algebra & Logic Gates

Common Postulates (Boolean Algebra) Closure N={1,2,3,4,5,..} It is closed w.r.t + i.e. a+b=c as a,b,cN Associative Law (x*y)*z = x*(y*z) for all x,y,z,S Commutative Law x*y = y*x for all x,yS x+y = y+x

x+y = y+x x.Y = y.x

Common Postulates (Boolean Algebra) Identity Element x+0 = 0+x = x x.1 = 1.x = x Inverse e*x = x*e = x e+x = x+e = x 0+x = x+0 = x 1*x = x*1 = x xS

a+(-a) = 0 Distributed Law x*(y.z) = (x*y) . (x*z) x.(y+z) = (x.y) + (x.z) x+(y.z) = (x+y) . (x+z)

x+x = 1 x*y = e a*1/a = 1 x+y = e x.x = 0

Boolean Algebra and Logic Gatesx 0 0 1 1 y 0 1 0 1 x.y 0 0 0 1 x 0 0 1 1 y 0 1 0 1 x+y 0 1 1 1 x 0 1 x 1 0

x.(y+z) = (x.y)+(x.z)x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Y+z 0 1 1 1 0 1 1 1 x.(y+z) 0 0 0 0 0 1 1 1 x.y 0 0 0 0 0 0 1 1 x.z 0 0 0 0 0 1 0 1 (x.y)+x.z 0 0 0 0 0 1 1 1

Postulates and Theorems of Boolean AlgebraPostulate 2 Postulate 5 Theorem 1 Theorem 2 Theorem3, involution Postulate3, commutative Theorem4, associative Postulate4, distributive Theorem5, DeMorgan Theorem6, absorption (a) x+0 = x (a) x+x = 1 (a) x+x = x (a) x+1 = 1 (x) = x (a) x+y = y+x (a) x+(y+z)=(x+y)+z (a) x(y+z)=xy+xz (a) (x+y) = xy (a) x+xy = x (b) xy = yx (b) x(yz) = (xy)z (b) x+yz = (x+y)(x+z) (b) (xy) = x+y (b) x(x+y)=x (b) x.1 = x (b) x.x = 0 (b) x.x = x (b) x.0 = 0

Theorems1a. x+x = x x+x = (x+x).1 = (x+x)(x+x) = x+xx =x+0 =x x.x = x (Remember Duality of 1a) x.x = xx+0 = xx+xx = x(x+x) = x.1 =x

1b.

Theorems2a. x+1 = 1 x+1 =1.(x+1) = (x+x)(x+1) = (x+x) = x+x =1 X.0 = 0 (Remember Duality of of

2b. 2a)

3.

6a

6b.

(x) = x Complement of x = x Complement of x = (x) = x x+xy = x x+xy = x.1+xy = x(1+y) = x.1 =x x(x+y) = x (Remember Duality of 6a)

Can also be proved using truth table method

x 0 0 1 1

y 0 1 0 1 x=x+xy

xy 0 0 0 1

x+xy 0 0 1 1

x 0 0 1 1

y 0 1 0 1

x+y 0 1 1 1

(x+y) 1 0 0 0

x 1 1 0 0

y 1 0 1 0

xy 1 0 0 0

(x+y) = xy DeMorgans Theorem (xy) = x +y DeMorgans Theorem

Operator Precedence 2.( ) 3.NOT 4.AND 5.OR

x xy xy xy

y

x

y

xyVENN DIAGRAM FOR TWO VARIABLES VENN DIAGRAM ILLUSTRATION X=XY+X

x

y

x

y

z x+(y+z) xy+xz

z

VENN DIAGRAM ILLUSTRATION OF THE DISTRIBUTIVE LAW

TRUTH TABLE FOR F1=xyz, F2=x+yz, F3=xyz+xyz+xy and F4=xy+xzx 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F1 0 0 0 0 0 0 1 0 F2 0 1 0 0 1 1 1 1 F3 0 1 0 1 1 1 0 0 F4 0 1 0 1 1 1 0 0

z x y F1 y z x F2

(a) F1 = xyzx

(b) F2 = x+yz

y

z

F3

(c) F3 = xyz+xyz+xy

x y

F4

z

(c) F4 = xy+xz

Implementation of Boolean Function with GATES

Algebraic Manipulations for Minimization of Boolean Functions (Literal minimization)

1.

x+xy = (x+x)(x+y) = 1.(x+y)=x+y 3. x(x+y) = xx+xy = 0+xy=xy 5. xyz+xyz+xy = xz(y+y)+xy = xz+xy 8. xy+xz+yz (Consensus Theorem) =xy+xz+yz(x+x) =xy+xz+xyz+xyz =xy(1+z)+xz(1+y) =xy+xz 13. (x+y)(x+z)(y+z)=(x+y)(x+z) by duality from function 4

Complement of a Function(A+B+C) = (A+X) = AX = A.(B+C) = A.(BC) = ABC (A+B+C+D+..Z) = ABCD..Z (ABCD.Z) = A+B+C+D+.+Z Example using De Morgans Theorem (Method-1) F1 = xyz+xyz F1 = (xyz+xyz) = (x+y+z)(x+y+z) F2 = x(yz+yz) F2= [x(yz+yz)] = x+(y+z)(y+z)

Example using dual and complement of each literal (Method-2)

F1 = xyz + xyzDual of F1 = (x+y+z)(x+y+z) Complement F1 = (x+y+z)(x+y+z) F2 = x(yz+yz) Dual of F2=x+(y+z)(y+z] Complement =F2= x+ (y+z)(y+z)

Minterm or a Standard Product n variables forming an AND term provide 2n possible combinations, called minterms or standard products (denoted as m1, m2 etc.). Variable primed if a bit is o Variable unprimed if a bit is 1 Maxterm or a Standard Sum n variables forming an OR term provide 2n possible combinations, called maxterms or standard sums (denoted as M1,M2 etc.). Variable primed if a bit is 1 Variable unprimed if a bit is 0

MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES MINTERMS x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Term xyz xyz xyz xyz xyz xyz xyz xyz Designation m0 m1 m2 m3 m4 m5 m6 m7 MAXTERMS Term x+y+z x+y+z x+y+z x+y+z x+y+z x+y+z x+y+z x+y+z Designation M0 M1 M2 M3 M4 M5 M6 M7

FUNCTION OF THREE VARIABLESx 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Function f1 0 1 0 0 1 0 0 1 Function f2 0 0 0 1 0 1 1 1

f1 = xyz+xyz+xyz =m1 + m4 + m7 f2 = xyz+xyz+xyz+xyz = m3 + m5 + m6 + m7

MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES

f1 = xyz+xyz+xyz f1 = xyz+xyz+xyz+xyz+xyz f1 =(x+y+z)(x+y+z)(x+y+z)(x+y+z) (x+y+z) = M0.M2.M3.M5.M6 = M0M2M3M5M6 f2 = xyz+xyz+xyz+xyz f2 = xyz+xyz+xyz+xyz f2 = (x+y+z)(x+y+z)(x+y+z)(x+y+z) = M0 M1 M2 M4 Canonical Form Boolean functions expressed as a sum of minterms or product of maxterms are said to be in canonical form. M3+m5+m6+m7 or M0 M1 M2 M4

Sum of Minterms (Sum of Products)Example: F = A+BC F = A(B+B)+BC(A+A) = AB+AB+ABC+ABC = AB(C+C)+AB(C+C)+ABC+ABC = ABC+ABC+ABC+ABC+ABC+ABC = ABC+ABC+ABC+ABC+ABC = m1+m4+m5+m6+m7 F(A,B,C)=(1,4,5,6,7)

ORing of term

AND terms of variables A,B &C They are minterms of the function

Product of Maxterms (Product of sums)Example: F = xy+xz F = xy+xz F = (xy+x)(xy+z) distr.law (x+yz)=(x+y)(x+z) = (x+x)(y+x)(x+z)(y+z) = (x+y)(x+z)(y+z) = (x+y+zz)(x+z+yy)(y+z+xx) = (x+y+z)(x+y+z)(x+z+y)(x+z+y)(y+z+x)(y+z+x) = (x+y+z)(x+y+z)(x+y+z)(x+y+z) = M0 M2 M4 M5 F(x,y,z) = (0,2,4,5) ANDing of terms Maxterms of the function (4 OR terms of variables x,y&z)

Conversion between Canonical FormsF(A,B,C) = (1,4,5,6,7) sum of minterms F(A,B,C) = (0,2,3) = m0+m2+m3 F(A,B,C) = (m0+m2+m3) = m0.m2.m3 = M0 M2 M3 = (0,2,3) Product of maxterms Similarly F(x,y,z) = (0,2,4,5) F(x,y,z) = (1,3,6,7)

Standard FormsSum of Products (OR operations) F1 = y+xy+xyz (AND term/product term) Product of Sums (AND operations) F2=x(y+z)(x+y+z+w)

(OR term/sum term) Non-standard form F3=(AB+CD)(AB+CD) Standard form of F3 F3=ABCD + ABCD

TRUTH TABLE FOR THE 16 FUNCTIONS OF TWO BINARY VARIABLESx 0 0 1 1 y 0 1 0 1 F0 0 0 0 0 F1 0 0 0 1 F2 0 0 1 0 F3 0 0 1 1 F4 0 1 0 0 F5 0 1 0 1 F6 0 1 1 0 F7 0 1 1 1 + F8 1 0 0 0 F9 1 0 0 1 F10 1 0 1 0 , F11 1 0 1 1 F12 1 1 0 0 , F13 1 1 0 1 F14 1 1 1 0 F15 1 1 1 1

Operator symbols

F0 = 0 F4 = xy F8 = (x+y) F12 = x

F1 = xy F5 = y F9 = xy +xy F13 = x + y

F2 = xy F6 = xy +xy F10 = y F14 = (xy)

F3 = x F7= x +y F11 = x +y F15 = 1

BOOLEAN EXPRESSIONS FOR THE 16 FUNCTIONS OF TWO VARIABLEBOOLEAN FUNCTIONS F0 =0 F1=xy F2=xy F3=x F4=xy F5=y F6=xy+xy F7=x+y F8=(x+y) F9=xy+xy F10=y F11=x+y F12=x F13=x+y F14=(xy) F15=1 x.y x/y y/x x y x+y x y x y y xy x xy x y OPERATOR SYMBOL NAME NULL AND inhibition transfer inhibition transfer exclusive-OR OR NOR *equivalence complement implication complement implication NAND IDENTITY COMMENTS BINARY CONSTANT 0 x and y x but not y x y but not x y x or y but not both x or y not OR x equals y not y if y then x not x if x then y not AND BINARY CONSTANT 1

*Equivalence is also known as equality, coincidence, and exclusive NOR 16 logic operations are obtained from two variables x &y Standard gates used in digital design are: complement, transfer, AND, OR , NAND, NOR, XOR & XNOR (equivalence).

H and L LEVEL IN IC LOGIC FAMILIESIC Family Voltage High-level voltage Low-level Type Supply (V) (V) voltage (V)

Range

Typical

Range

Typical

TTL Vcc=5 2.4-5 3.5 ECL VEE=-5.2 -0.95- -0.7 -0.8 CMOS VDD=3--10 VDD VDD Positive Logic: Logic-1 Negative Logic Logic-0

0-0.4 0.2 -1.9-- -1.6 -1.8 0-0.5 0 Logic-0 Logic-1

TYPICAL CHARACTERISTICS OF IC LOGIC FAMILIESIC Logic Family Standard TTL Shottky TTL Low power Shottky TTL ECL CMOS 10 10 20 25 50 Fan out Power Dissipation (mw) 10 22 2 25 0.1 Propagation delay (ns) 10 3 10 2 25 Noise Margin (v) 0.4 0.4 0.4 0.2 3

TTL basic circuit : NAND gate ECL basic circuit: NOR gate CMOS basic circuit: Inverter to construct NAND/NOR

DIGITAL LOGIC GATESNAME GRAPHIC SYMBOL ALGEBRIC FUNCTION F=XY X Y F TRUTH TABLE X Y 0 0 0 1 1 0 1 1 X Y 0 0 0 1 1 0 1 1 F 0 0 0 1 F 0 1 1 1 AND

OR X Y F

F=X+Y

NAME Inverter X Buffer X

GRAPHIC SYMBOL

ALGEBRIC FUNCTION X 0 1 X 0 1

TRUTH TABLE F 1 0 F 0 1

F

F=X

F

F=X

NAND

X Y

F

F=(XY)

X Y 0 0 0 1 1 0 1 1

F 1 1 1 0

NAME

GRAPHIC SYMBOL X Y

ALGEBRIC FUNCTION

TRUTH TABLE X Y 0 0 0 1 1 0 1 1 X Y 0 0 0 1 1 0 1 1 X Y 0 0 0 1 1 0 1 1 F 1 0 0 0 F 0 1 1 0 F 1 0 0 1

NOR

F

F=(X+Y)

Exclusive-OR (XOR)

X Y

F

F=XY+XY =XY

Exclusive-NOR or Equivalence

X Y

F

F=XY+XY =X Y

x Y Z

(X+Y) [Z+(X+Y)] (X Y) Z=(X+Y) Z =XZ+YZ

X

(X ( Y Z)=X(Y+ Z) =XY+XZ [X+(Y+Z)] Y Z (Y+Z)

Demonstrating the nonassociativity of the NOR operator (X Y) Z X (Y Z)

X Y Z

(X+Y+Z)

X Y Z

(XYZ)

(a) There input NOR gate

(b) There input NAND gate

A B C F=[(ABC). (DE)]=ABC+DE D E (c) Cascaded NAND gates

Multiple-input AND cascaded NOR and NAND gates

TRUTH TABLE X Y X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 0 1 1 0 1 0 0 1 XOR F=X Y Z XNOR (b) Three input gates Odd function Even function 1 0 0 1 0 1 1 0

Z

F=X Y Z

(a) Using two input gates X Y Z

(b) Three input exclusive OR gates

IC DIGITAL LOGIC FAMILIESTTL Transistor- Transistor Logic

Very popular logic family. It has a extensive list of digital functions. It has a large number of MSI and SSI devices, also has LSI devices.ECL Emitter Coupled Logic

MOS Metal-Oxide Semiconductor

Used in systems requiring high speed operations. It has a large number of MSI and SSI devices, also LSI devices. Used in circuit requiring high component density It has a large number of MSI and SSI devices, also LSI devices (mostly) Used in systems requiring low power consumption. It has a large number of MSI and SSI devices, also has LSI devices. Used in circuit requiring high component density. Mostly used for LSI functions

CMOS Complementary MOS

I2L Integrated - Injection Logic

Some Typical IC GatesVCC14 13 12 11 10 9 8

VCC14 13 12 11 10 9 8

1

2

3

4

5

6

7

1

2

3

4

5

6

7

GND

GND

7404 Hex Inverters

7400 Quadruple 2-input NAND gates

TTL gates

VCC 2 16 15

Some Typical IC Gates14 13 12 11 10 9

10107 Triple Exclusive OR/ NOR gates

1 2 VCC 1 VCC 2 16

3

4

5

6

7

8

VEE 2 (-5.2V)

15

14

13

12

11

10

9

10102 Quadruple 2-Input NOR gate

VCC 1

1

2

3

4

5

6

7

8

VEE (-5.2V)

VDD 14 13

(3-15 V) 12 11 10 9

NC 8

C MOS GATES

1

2

3

4

5

6 NC

7 Vss (GND)

4002 dual 4 input NOR gates

NC 16 15 14

NC 13 12 11 10 9

CMOS GATES 1 2 3 4 5 6 7 8 Vss (GND) VDD (3-15 V)

4050 Hex buffer

LOGIC VALUE 1

SIGNAL VALUE H

LOGIC VALUE 0

SIGNAL VALUE

H

0

L Positive Logic

1 Negative Logic

L

Signal amplitude assignment and type of logic

X L L H H

y L H L H

z H H H L Gate block diagram y x TTL 7400 GATE z

Truth table in terms of H and L X 0 0 1 1 y 0 1 0 1 z 1 1 1 0

x y

z

Truth table for positive logic H=1, L=0

Graphic symbol for positive logic NAND gate

X 1 1 0 0

y 1 0 1 0

z 0 1 1 1

x y

z

Graphic symbol for negative logic NOR gate

Truth table for negative logic L=1 H=0 Same gate can function +ive logic NAND or -ive logic NOR +ive logic NOR or -ive logic NAND

DEMONSTRATION OF POSITIVE AND NEGATIVE LOGIC

Characteristics of IC logic families (parameters)Fan-out Specifies the number of standard loads (the amount of current needed by an input of another gate in the same IC family) that the output of a gate can drive without impairing its normal operation. it is expressed by a number. Power dissipation It is the supplied power required to operate the gate. It is expressed in mw. Propagation delay It is the average transition delay time for a signal to propagate from input to output when the binary signals change in value. It is expressed in ns. Noise margin It is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts (v).