ΚΥΚΛΩΜΑΤΑ ECL (Emitter Coupled Logic)”ιάλεξη... · (Emitter Coupled Logic) ECL...
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ECL(Emitter Coupled Logic) ECL
(Emitter Coupled Logic)
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The Current Switch ( )The Current Switch ( )
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ECL
ECLQ1, Q2 =Rc=matched
: v Vref v > Vref ( mV)=> IEE Q1 v < Vref ( mV)=> IEE Q2
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:
=>
VBE2>= VBE1 +300 mVolts => VBE =-0.3 V VT=0.025 V => ic2> ic1 1.6x 105 ic1 VBE1>= VBE2 +300 mVolts current switch VBE mV
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/ - ic1,ic2 . ic, VBE :
=>:
:
: 99%
=> ECL
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(Vi> VREF) (Vi> VREF)
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=> +0.3 V = - Q1 => Q1= VBE=0.7 V Q2 = Off (Ic2=0) . KVL :
=>
=> VBE2=0.4 =>VBE2 - VBE1= 300 mV Q1, Q2= (VBE2=0.4) ? ( VC>VB?) :
=>
F1=>
=>Vc1= - 0.6 V , Vc2= 0V Q1, Q2= =>
2 Q2
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(Vi< VREF) (Vi< VREF)
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-0.3 V => Q2 => Q2= VBE=0.7 V Q1 = Off (Ic1=0) . KVL :
=>
=>
=>
: iE10 , iE2 iEE ( U1< U2) Q1, Q2 = Q1: C1=0 > B1= I=-1.3 V Q2: C2=-0.6> B2= VREF= -1 V
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(0 -0.6V) 1 0 .: ( ) : 0.7 V , : transistors
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(ECL) (ECL)
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:
=>
:
=> F > 20=> ib Rc
Q3 , Q4= Q3: C3=0 > B3= c1=-0.6 V Q4 : C4=0>= B4=c2=0 V=> BE3 = BE4 = 0.7 Volts
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(ECL) (ECL)
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:
=>
ECL : MOSFETiIN= Q1 . Q1= OFF (I=-1.3 V)=> iIN= 0, Q1= =>
:
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(ECL) (ECL)
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= . I= => 01= ( ) 01=
VREF :
(swings) VREF =0.3 V . :
:
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ECL ECL
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ECL VIH , VIL- = -1 1 . 01 :
ic1vs :
:
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ECL ECL
KVL
=> =>
=>
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ECL ECL
= =>
=>
VIH :
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ECL ECL
=>
=>
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ECL ECL
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IEE IEE
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(ECL) (ECL)
-: ECL =>
transistors transistor ( V /
To transistor OFF= VBE = Volt
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ECL OR-NOR ECL OR-NOR
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AND / ORO ECL = OR-NOR => transistors transistor .. (, , C) = (I > VREF => () CI => 1= Low, 1= High=> 1= NOR 1= OR =>
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ECL OR-NOR ECL OR-NOR
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ECL .. NOR=> OR Q2 ,
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ECL OR-NOR ECL OR-NOR
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OR=> NOR
Q transistors , ,
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Wired OR Wired OR
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, ECL=> . Q1 transistor . Q2
: , Q2 = , => VBE2= 0.7 . VB2=-0.6=> VE2=VE = -1.3. VBE1 =1.3 VBE > 0.7 => VBE1=0.7=> VE1=VE2= VE= 0.7 ( VB1=0) => VBE2 =VB2- VE= -0.6- (-0.7)= 0.1=> Q2 = Q2= OFF=> i1= 2IEE => Q1
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Wired OR Wired OR
Wired OR
, OR.
, . , = High, => OR =+.
ECL
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Wired OR Wired OR
Wired OR ECL
Wired-OR. H NOR OR
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Wired OR wired NAND Wired OR wired NAND
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, OR NAND
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(single-sided) ECL (single-sided) ECL
ECL single-sided =current switch ( ) (Vref ) 0 1
ECL (subnanosecs !) VLSI !
: 300 MHz 32-bit microprocessor 486 =115 W!
ECL
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ECL ECL
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ECL : Vref current switch 1, Vin voltage swing=> switching , effective voltage swing ECL
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ECL ECL
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ECL = voltage swing. :
Vin=> , c1= 99% ( Vin= VIH Vin =VIL)
: voltage swing 2 (single-ended) ECL => voltage swing . voltage swing 200 mV
=> =
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CML (Current Mode Logic) CML (Current Mode Logic)
differential ECL => => Current Mode Logic (CML) IEE ( ) (differential ) (stacking current switch pairs)
current steering (IEE ) ,
:
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CML (AND/NAND )CML (AND/NAND )
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, 1 => IEE Q1 Q3 RC1 => ( Q3 ), = = => = = () => AND-NAND
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CML - /CML - /
Now let us find the voltage levels in this circuit. At the output, IEE appears in one collector resistor, and zero current
is in the other collector resistor. Thus the two logic levels are :VH = 0 V and VL = IEE RC. In CML circuits, VL is often chosen to be 400 mV, which is more
than enough to completely switch the currents with good noise margin.
The logic levels are centered around: (VH + VL)/2 = 200 mV.
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CML (OR/NOR )CML (OR/NOR )
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( OR/NOR : Z (0), Z (1) A B (1) Z = A B= (A + B ) Z = A + B.
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CML CML
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: () OR/NOR 6 transistors single-ended ( . Vref ) 4 transistors , differential ECL (CML)
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CML -CML -
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CML = transistors => DC =VBE (on)
= ()
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CML -CML -
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= = emitter followers . emitter follower VBE (on). => DC 3-4 CML Vcc- N *VBE (on), Vin = Level N
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CML -CML -
This level-shifting creates extra complexity, since multiple wires
may need to be routed for the same signal, depending upon the fan-out of the gate.
It also puts a restriction on the number of transistors that can be stacked.
The propagation delay is a function of the output level, because signals lower on the stack have a higher delay.
Adding too many layers results in an intolerable performance degradation
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CML - CML -
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Another way to address non compatible signal levels, while avoiding the complex multilevel output emitter-follower, is to insert level-shifting circuits whenever needed. A level 1-to-level 2 converter is shown in Figure . In this way, all standard logic gates can be designed with a sole level 1 output, and level-shifting buffers are introduced only when connecting to multilevel gates.
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CML CML
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Examples of complex CML logic gate implementations is the CML D-latch shown in Figure aboveNote that the storage element of the latch is formedby the cross-coupled inverter pair formed by Q5, Q6 and the two collector resistors. When the CLK input is high, the output tracks the D input; the outputs are latched when CLK goes low.
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NMOS CML NMOS CML
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H CML NMOS differential ECL. H VH= 0 Vlow= - IEE RD
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NMOS CML NMOS CML
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It is easy to prove correct functionality by tracing out the currentflow. For instance, in the OR gate, (Fig.A) if A is high, then the current must flow through M2 and M5 (note that M5 is included for level matching), pulling the negative output low and, thus, producing logic one. If A is low, then B determines the output. With the differential CML topology, the CML AND gate is exactly thesame as the CML OR gate in structure (Figure (b)), but the input and output polarities are changed. This is not surprising, as DeMorgans law points out that
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NMOS CML NMOS CML
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XOR gate.
As a XOR gate, it can be shown that if either A or B, but not both, is high, a logic one is the result
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XOR BJT CML XOR BJT CML
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NMOS CML
