A new dynamical approach of Emden-Fowler equations and systems
Impact of metal work function on memory properties of charge-trap flash memory devices using...
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486 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 6, JUNE 2006 Impact of Metal Work Function on Memory Properties of Charge-Trap Flash Memory Devices Using Fowler–Nordheim P/E Mode Sanghun Jeon, Member, IEEE, Jeong Hee Han, Junghoon Lee, Sangmoo Choi, Hyunsang Hwang, and Chungwoo Kim Abstract—This letter reports the impact of metal work func- tion (Φ M ) on memory properties of charge-trap-Flash memory devices using Fowler–Nordheim program/erase mode. For elimi- nating electron back tunneling and hole back tunneling through the blocking oxide during an program/erase operation, a gate with Φ M of 5.1–5.7 eV on an Al 2 O 3 –SiN–SiO 2 (ANO) stack is necessary. Compared to a thickness optimized n + poly-Si/ONO stack, a high-work-function gate on an ANO stack shows dramatic improvements in retention versus minimum erase state. Index Terms—Charge trap, electron back tunneling (EBT), hole back tunneling (HBT), work function. F LOATING gate interference among adjacent cells is known to be a critical obstacle in sub-50-nm NAND- type floating-gate Flash memory devices [1]. Thus, charge- trap Flash (CTF) memory devices have received a considerable attention in recent years. CTF devices have several advantages including fast programming, low-power operation, high-density integration, and good reliability characteristics [2]–[4]. How- ever, it is difficult to simultaneously satisfy NAND specifications of low-erase state (V th = −3 V after −18 V, 2-ms pulse) and good retention characteristics (∆V th less than 0.3 V at 85 ◦ C for ten years) because the current through the tunnel dielectric critically affects both properties and electron back-tunneling (EBT) effect. To reconcile this conflicting behavior, we have carried out a systematic study on the impact of metal work function (Φ M ) on the memory properties of CTF devices using both experi- mental and theoretical methods. For the theoretical approach, V. A. Gritsenko’s model was used [5]. Manuscript received February 14, 2006. This work was supported by Tera- level Nano Devices program through the Ministry of Science and Technology, Korea. The review of this letter was arranged by Editor A. Chatterjee. S. Jeon was with the Devices Laboratory, Samsung Advanced Institute of Technology (SAIT), Gyunggi-do 449-712, Korea. He is now with the Ad- vanced Technology Team of Semiconductor R&D Center, Memory Business, Samsung Electronics Company, Ltd. Gyunggi-do 449-711, Korea (e-mail: [email protected]). J. H. Han and C. Kim were with the Devices Laboratory, SAIT, Gyunggi-do 449-712, Korea. They are now with the Process Development Team of Semi- conductor R&D Center, Memory Business, Samsung Electronics, Gyunggi-do 449-711, Korea. J. Lee is with the Devices Laboratory, SAIT, Gyunggi-do 449-712, Korea. S. Choi and H. Hwang are with the Department of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), Gwangju 500-712, Korea. Digital Object Identifier 10.1109/LED.2006.874216 MOS capacitors with various stacks were fabricated using conventional Si processes. SiO 2 –SiN–SiO 2 (ONO) and Al 2 O 3 –SiN–SiO 2 (ANO) stacks were prepared. Tunnel SiO 2 was grown by a thermal oxidation in O 2 at 850 ◦ C and postannealed in N 2 O at 850 ◦ C. For a better program and erase speed, Si-rich SiN as a trapping layer was prepared by adjusting the ratio of Dichlorosilane (DCS) to NH 3 in a low-pressure chemical vapor deposition (LPCVD) system. For ONO devices, blocking SiO 2 was deposited by LPCVD process. For compar- ison, Al 2 O 3 films were deposited by an atomic layer deposition (ALD) system. To study the effect of Φ M without unwanted side effects, various metal gates (Al, TiAl, Pd, Au, and Pt) on ANO stack were deposited by e-beam evaporation at room temperature. To determine the Φ M of metal gates, dielectrics of various thickness were used and calculated by V FB versus 1/C ox plots. In our experiments, the Φ M of Al, TiAl, Pd, Au, and Pt was found to be 4.1, 4.6, 4.9, 5.1, and 5.7 eV, respec- tively. Most noble metals having high Φ M are fast diffusers with a high solubility in Si, degrading transistor performance. However, from our study, the information of appropriate work- function gates for CTF devices can be supplied. Simulation studies were also performed for an ONO stack with respect to Φ M . In this simulation [5], a one-dimensional two-band model of a charge transport was used and double carrier injection from both the silicon substrate and opposite electrode was consid- ered. For trap population, the Shockley–Read–Hall method was used. The charged state was characterized by V th , which was extracted from V FB of MOS capacitors. In our system, calcu- lated V th was typically V FB +0.5 V. Based on the acceleration factor used in our retention study, a 250 ◦ C, 2-h bake condition was found to be equivalent to an 85 ◦ C, ten-year condition for V th shift. Fig. 1 shows the erase characteristics of an n + poly-Si/ONO stack. By applying a higher erase voltage on the gate, electrons trapped in the nitride layer can be displaced more quickly. However, at higher erase voltages, electrons can tunnel from the gate into the nitride layer. This phenomenon is referred to as “EBT” [6], [7] and is the result of a low-electron barrier height in the band diagram at the ONO/gate. Due to “back tunneling,” the effectiveness of a high erase voltage is saturated and it may not be possible for the device to reach its fully “erased” state. To investigate the effect of Φ M on erase characteristics of ONO, simulation studies were performed. This was done to eliminate unwanted side effects such as poor adhesion of a 0741-3106/$20.00 © 2006 IEEE
Transcript of Impact of metal work function on memory properties of charge-trap flash memory devices using...
486 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 6, JUNE 2006
Impact of Metal Work Function on MemoryProperties of Charge-Trap Flash Memory Devices
Using Fowler–Nordheim P/E ModeSanghun Jeon, Member, IEEE, Jeong Hee Han, Junghoon Lee, Sangmoo Choi,
Hyunsang Hwang, and Chungwoo Kim
Abstract—This letter reports the impact of metal work func-tion (ΦM ) on memory properties of charge-trap-Flash memorydevices using Fowler–Nordheim program/erase mode. For elimi-nating electron back tunneling and hole back tunneling throughthe blocking oxide during an program/erase operation, a gatewith ΦM of 5.1–5.7 eV on an Al2O3–SiN–SiO2 (ANO) stack isnecessary. Compared to a thickness optimized n+ poly-Si/ONOstack, a high-work-function gate on an ANO stack shows dramaticimprovements in retention versus minimum erase state.
Index Terms—Charge trap, electron back tunneling (EBT), holeback tunneling (HBT), work function.
F LOATING gate interference among adjacent cells isknown to be a critical obstacle in sub-50-nm NAND-
type floating-gate Flash memory devices [1]. Thus, charge-trap Flash (CTF) memory devices have received a considerableattention in recent years. CTF devices have several advantagesincluding fast programming, low-power operation, high-densityintegration, and good reliability characteristics [2]–[4]. How-ever, it is difficult to simultaneously satisfy NAND specificationsof low-erase state (Vth = −3 V after −18 V, 2-ms pulse) andgood retention characteristics (∆Vth less than 0.3 V at 85 ◦Cfor ten years) because the current through the tunnel dielectriccritically affects both properties and electron back-tunneling(EBT) effect.
To reconcile this conflicting behavior, we have carried out asystematic study on the impact of metal work function (ΦM )on the memory properties of CTF devices using both experi-mental and theoretical methods. For the theoretical approach,V. A. Gritsenko’s model was used [5].
Manuscript received February 14, 2006. This work was supported by Tera-level Nano Devices program through the Ministry of Science and Technology,Korea. The review of this letter was arranged by Editor A. Chatterjee.
S. Jeon was with the Devices Laboratory, Samsung Advanced Institute ofTechnology (SAIT), Gyunggi-do 449-712, Korea. He is now with the Ad-vanced Technology Team of Semiconductor R&D Center, Memory Business,Samsung Electronics Company, Ltd. Gyunggi-do 449-711, Korea (e-mail:[email protected]).
J. H. Han and C. Kim were with the Devices Laboratory, SAIT, Gyunggi-do449-712, Korea. They are now with the Process Development Team of Semi-conductor R&D Center, Memory Business, Samsung Electronics, Gyunggi-do449-711, Korea.
J. Lee is with the Devices Laboratory, SAIT, Gyunggi-do 449-712, Korea.S. Choi and H. Hwang are with the Department of Materials Science and
Engineering, Gwangju Institute of Science and Technology (GIST), Gwangju500-712, Korea.
Digital Object Identifier 10.1109/LED.2006.874216
MOS capacitors with various stacks were fabricated usingconventional Si processes. SiO2–SiN–SiO2 (ONO) andAl2O3–SiN–SiO2 (ANO) stacks were prepared. Tunnel SiO2
was grown by a thermal oxidation in O2 at 850 ◦C andpostannealed in N2O at 850 ◦C. For a better program and erasespeed, Si-rich SiN as a trapping layer was prepared by adjustingthe ratio of Dichlorosilane (DCS) to NH3 in a low-pressurechemical vapor deposition (LPCVD) system. For ONO devices,blocking SiO2 was deposited by LPCVD process. For compar-ison, Al2O3 films were deposited by an atomic layer deposition(ALD) system. To study the effect of ΦM without unwantedside effects, various metal gates (Al, TiAl, Pd, Au, and Pt)on ANO stack were deposited by e-beam evaporation at roomtemperature. To determine the ΦM of metal gates, dielectricsof various thickness were used and calculated by VFB versus1/Cox plots. In our experiments, the ΦM of Al, TiAl, Pd, Au,and Pt was found to be 4.1, 4.6, 4.9, 5.1, and 5.7 eV, respec-tively. Most noble metals having high ΦM are fast diffuserswith a high solubility in Si, degrading transistor performance.However, from our study, the information of appropriate work-function gates for CTF devices can be supplied. Simulationstudies were also performed for an ONO stack with respect toΦM . In this simulation [5], a one-dimensional two-band modelof a charge transport was used and double carrier injection fromboth the silicon substrate and opposite electrode was consid-ered. For trap population, the Shockley–Read–Hall method wasused. The charged state was characterized by Vth, which wasextracted from VFB of MOS capacitors. In our system, calcu-lated Vth was typically VFB + 0.5 V. Based on the accelerationfactor used in our retention study, a 250 ◦C, 2-h bake conditionwas found to be equivalent to an 85 ◦C, ten-year condition forVth shift.
Fig. 1 shows the erase characteristics of an n+ poly-Si/ONOstack. By applying a higher erase voltage on the gate, electronstrapped in the nitride layer can be displaced more quickly.However, at higher erase voltages, electrons can tunnel fromthe gate into the nitride layer. This phenomenon is referred to as“EBT” [6], [7] and is the result of a low-electron barrier heightin the band diagram at the ONO/gate. Due to “back tunneling,”the effectiveness of a high erase voltage is saturated and it maynot be possible for the device to reach its fully “erased” state.
To investigate the effect of ΦM on erase characteristics ofONO, simulation studies were performed. This was done toeliminate unwanted side effects such as poor adhesion of a
0741-3106/$20.00 © 2006 IEEE
JEON et al.: IMPACT OF METAL WORK FUNCTION ON MEMORY PROPERTIES OF CTF MEMORY DEVICES 487
Fig. 1. Erase characteristics of n+poly-Si/ONO structure. The thickness ofblock SiO2, trapping SiN, and tunnel SiO2 was 80, 50, and 25 Å, respectively.At higher erase bias, EBT was observed due to the low-electron barrier height.
Fig. 2. Simulation results; minimum erase Vth of ONO stack versus appliederase bias with pulsewidth of 2 ms with respect to metal work function (ΦM ).By increasing ΦM , EBT was dramatically reduced and erase efficiency wasimproved.
high-ΦM gates on SiO2 and so on. As shown in Fig. 2, min-imum erase Vth versus applied erase bias with a pulse time of2 ms was plotted with respect to different ΦM . For a gate withΦM of 4.1 eV, poor erase characteristics were observed due tothe low-electron barrier height. However, with increasing ΦM ,dramatic improvements in erase characteristics were achieveddue to the increasing electron barrier height. Thus, the high-ΦM
gate is crucial in attaining the minimum erase state Vth whilenot affecting program characteristics. However, even with arelatively thin tunnel SiO2 used in the simulation study of Fig. 2and experimental results (not shown), attaining an erase stateVth value of less than −3 V with the given erase condition wasstill difficult using ONO stack. This motivated us to incorporatehigh-κ dielectrics for the blocking dielectric. In our study,Al2O3 was used as a blocking dielectric due to its thermalstability and well-understood material properties, As shown inFig. 3, the dependence of erase characteristics on ΦM was alsoexperimentally found to be very strong for ANO stacks, whichis possibly due to the lower electron barrier height of Al2O3.For a gate with ΦM of 4.1 eV, erase operation actually increasesthe Vth. Similar to the simulation results of ONO stack, withincreasing ΦM , EBT is dramatically reduced. To eliminate theEBT effect, ΦM of more than 5.1 eV is appropriate for the ANOstack used in our investigation. For ΦM of larger than 5.1 eV, asignificant difference of erase characteristics was not observed,
Fig. 3. Erase characteristics of different ΦM on ANO and erase bias condition(−14 to −18 V). With increasing ΦM , EBT was dramatically reduced. Toeliminate the EBT effect, ΦM larger than 5.1 eV was appropriate for the ANOstacks used in our investigation.
Fig. 4. Program and erase characteristics of high work function Au (ΦM of5.1 eV) and Pt (ΦM of 5.7 eV) metal gate on ANO. At high-program bias forthe long program time, HBT was observed for Pt-gate stack. Inset shows theenergy band diagram of ANO. The information of band alignment of Al2O3
was obtained by X-ray photoelectron spectroscopy (XPS) O1s loss spectrumand valence band spectrum. Both EBT in Fig. 3 and HBT can be explained bythe difference in a barrier height with respective ΦM .
as shown in Fig. 4. However, Pt (ΦM of 5.7 eV)-gated stackshows a different program behavior. At high-program bias for along program time, Pt stack shows hole back-tunneling (HBT)effect. This can be explained by a relatively low-hole barrierheight of Al2O3 and high ΦM Pt gate. HBT can be anotherissue for high-κ films with a lower bandgap (Eg) than Al2O3
as a blocking dielectric. Considering of the results of our study,and recent investigation on metal gate, TaN [8], TiAlN [9], andWN [10] can be strong candidates for CTF devices.
Compared to a conventional n+ poly-Si on thickness op-timized ONO stack, the high-ΦM gate on a various ANOstack was shown in a dramatic improvement in retention versuserasing characteristics in Fig. 5. By employing the high-ΦM
gate, the erase properties were improved and thus the thicknessof tunnel SiO2 could be further increased up to 4 nm. Relativelythick tunnel SiO2 offers better retention memory propertieswith still good erase characteristics. For endurance character-istics, low-ΦM -gate stacks to show poor erase properties arenot considered. Between Au- and Pt-gate stacks, we could not
488 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 6, JUNE 2006
Fig. 5. Retention characteristics at 250 ◦C, 2 h versus minimum eraseVth at −18 V, 2 ms. Compared to conventional n+ poly-Si stack onthickness optimized ONO, high-work-function gate on ANO shows dramaticimprovement.
find any noticeable variation of endurance characteristics (lessthan 0.3 V shift) up to 1E4 program/erase cycles.
In summary, we report the impact of ΦM on memory prop-erties of CTF devices. Experimental and simulation resultsdemonstrate a strong effect of ΦM on erase characteristics.To eliminate EBT and HBT through blocking oxide duringan erase/program operation, optimal values of both gate ΦM
and high-κ dielectric Eg are necessary. Compared to thicknessoptimized n+ poly-Si/ONO stacks, the high-ΦM gate on ANOstacks shows dramatic improvements in retention versus mini-mum erase state.
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