Noise Susceptibility of Delta-Vbe Temperature Sensors

in Highly Integrated Power Converters

Derek Murray

Research and Development

Powervation Ltd.

Cork, Ireland

derek.murray@powervation.com

Dr. Karl Rinne

Research and Development

Powervation Ltd.

Cork, Ireland

karl.rinne@powervation.com

Abstract—This paper introduces the detrimental effects of

voltage regulator noise on ΔVBE-based temperature sense

circuits. The work began when a significant temperature

reporting inaccuracy was observed on a commercial DC-DC

power conversion module. In the paper, the observed problem

will be discussed, and a Spice model presented which allows the

issue to be simulated. The main part of the work, however,

concentrates on a comprehensive experimental investigation of

the problem. Taking into account the findings of this

investigation, it was possible to significantly improve the

accuracy of ΔVBE temperature sense circuits even when exposed

to high levels of EMI. The paper concludes by offering

important design guidelines for both analog and applications

engineers when these high-precision temperature sense circuits

are used on power conversion circuits.

I. INTRODUCTION

In recent years, several cases have been presented where voltage regulators are causing severe near-field signal integrity issues on surrounding circuitry at the PCB level [1]-[3]. In those cases, digital circuits have been the victim, for example high-speed differential memory pairs or communication signals on server platforms. In the work discussed in this paper, an analog circuit is the victim, namely a high-precision ΔVBE temperature sense circuit. Figure 1 summarizes this temperature sensing technique [4], [5]. The base-emitter voltage, VBE, of an NPN transistor is well known to decrease linearly with temperature with a slope of about -2mV/K. This complementary-to-absolute-temperature (CTAT) voltage can be expressed as [5]:

𝑉𝐵𝐸 = 𝑉𝑔0 + 𝑘𝑇

𝑞 ln 𝐼𝐶 − ln 𝛼 − 𝑟. 𝑙𝑛(𝑇) (1)

where Vg0 is the extrapolated band-gap voltage of silicon (~1.205V), k is Boltzmann's Constant, q is the charge on an electron, T is the absolute temperature in degrees Kelvin, IC is the collector current, and α and r are transistor process-related parameters such as carrier mobility, impurity concentration, etc. The process-related parameters α and r mean that the VBE-T relationship will change for different transistors, or even transistors of the same type/batch, affecting the use of the

transistor as a temperature sensor. The ΔVBE method is used to solve this problem. The basic principle is that by switching two different bias currents to a diode-connected transistor and taking the difference between the generated base-emitter voltages, the resulting ΔVBE signal depends only on the ratio of the switched currents i.e. in this way, transistor process parameters are eliminated:

∆𝑉𝐵𝐸 = 𝑉𝐵𝐸2 − 𝑉𝐵𝐸1 = 𝑘𝑇

𝑞𝑙𝑛

𝐼𝐶2

𝐼𝐶1 (2)

where IC2 generates a base-emitter voltage VBE2, and IC1 generates a base-emitter voltage VBE1. The ΔVBE signal is proportional-to-absolute-temperature (PTAT), as shown in figure 1.

The advantages of this temperature sensing technique (high accuracy and linearity, simplicity, low cost, and interchangeability of different transistors) make it attractive for use on power conversion circuits. Figure 2 illustrates a simple representation of the application circuit being discussed in this paper. The commercial product is a single-phase 30A 12V-to-1.8V point-of-load (POL) synchronous buck regulator, implemented on a very small form-factor (25mm x 12.5mm) power module. The POL is controlled by the Powervation PV3012 auto-tuning digital controller. As well as providing advanced digital loop compensation techniques, this device offers communications ports and a range of precision telemetry features, with one such feature being ΔVBE

Figure 1. ΔVBE Concept

978-1-4799-2325-0/14/$31.00 ©2014 IEEE 552

temperature reporting. The device alternately drives the switched currents IC1 and IC2 to the external NPN sensor to generate the ΔVBE signal. On the controller, the ΔVBE signal is first passed through a signal conditioning circuit and then applied to an ADC; the resulting digital code is available for conversion to the equivalent temperature using defined firmware operations.

The temperature sense functionality is crucial to the application. Firstly, it provides over-temperature protection for the module to trigger a shut-down in the case of destructive thermal events. Secondly, it is placed close to the output inductor with the aim of providing a measure of its core temperature; the controller can then compensate for the temperature-dependent DC resistance of the inductor and improve output current reporting accuracy [6]. During early testing of the module, however, the critical issue as shown in figure 3 was discovered. As the load current is increased from no-load to the maximum rated value of 30A, the reported temperature (i.e. the ΔVBE signal converted to the equivalent temperature) deviates dramatically from the real temperature of the module, meaning that the temperature sensor was

unusable.

This paper details the work done in researching the main aspects of this problem. In Section II, a valid hypothesis of the error mechanism is outlined, where it is proposed that a DC shift of the ΔVBE signal is occurring due to power-stage switching noise. A Spice model based on the hypothesis will then be given in Section III, allowing the issue to be simulated. Measurements taken using the power module on which the issue was observed will then be presented in Section IV, and further measurements on a second test circuit will be given in Section V. The paper concludes by offering important design guidelines for both analog and application engineers when these high precision temperature sense circuits are used on power conversion circuits.

II. ERROR MECHANISM HYPOTHESIS

A. Noise Source and Coupling Mechanism

Several papers have been presented which summarize the main electromagnetic interference (EMI) sources related to DC-DC switching regulators [7]-[10]. Regarding the temperature-reporting issue being discussed in this paper, two main observations are important: (1) On the power module, the NPN sensor is placed close to the switching node/loop, which is a very strong source of both electric field (high dv/dt) and magnetic field (high di/dt) noise. (2) Of these two potential noise sources, only the di/dt noise will change significantly when load current changes, because the current magnitude in the high-side MOSFET varies in direct proportion to the output load current, IO. Thus it is proposed that the noise source is the di/dt event created due to the on-off current flow in the switching loop. Also, it follows that the noise transfer mechanism must be inductive (i.e. magnetic field) coupling from the switching loop to the NPN sensor loop. A simple expression for the coupled noise voltage is [11]:

𝑉𝑛 = 𝐿𝑀 𝑑𝐼𝐴

𝑑𝑡 (3)

where Vn is the noise voltage induced in the sensor circuit, dIA/dt is the current change in the switching loop when the high-side FET switches on/off, and LM is the mutual inductance between the two circuits (see figure 4(a)).

B. Effect on Victim Circuit

While the ΔVBE circuit uses the difference between two generated base-emitter voltages to derive the PTAT temperature signal, only a single CTAT VBE signal needs to be considered to understand the effects of noise on the sensor circuit. Predicting the effect of noise on this circuit is complicated by the fact that it is non-linear. Often a simple small-signal analysis can be used as a starting point, but this is not very useful in this case as the noise levels can be large e.g. > 100mV [12]. Also, a small-signal analysis may not reveal the full effects of the noise capacitor, Cn, which is an important component in the noise mechanism, as will be seen. Instead, a simple large-signal analysis can be used, as shown in figure 4 (c). The NPN transistor is replaced by its large-signal equivalent [13], a noise source is connected to the emitter, and the sensor output is taken from across the

Figure 2. Application Circuit and Noise Source

Figure 3. ΔVBE Temperature reporting issue

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capacitor (as happens in the application circuit). The collector current, IC, in this circuit is given by:

𝐼𝐶 = 𝐼𝑆𝑒𝑉𝐵𝐸/𝑉𝑇 (4)

where IS is the transistor saturation current in A, VBE is the base-emitter voltage in V, and VT is the thermal voltage, kT/q (about 25.8mV at 300K), those parameters having been defined earlier. Differentiating equation 4 gives the transconductance, gm:

𝑔𝑚 = 𝑑𝐼𝐶

𝑑𝑉𝐵𝐸 =

𝐼𝑆

𝑉𝑇𝑒𝑉𝐵𝐸/𝑉𝑇 (5)

Now if we consider the inverse of the transconductance, 1/gm, the circuit in figure 4(c) can be viewed as a low-pass filter. The frequency plot in figure 4(c) indicates that the cut-off frequency of this filter will decrease as capacitor value is increased, as expected in a low-pass circuit. Now, depending on the magnitude and frequency of the injected noise, a 'soft' rectification effect can occur, causing a DC shift away from the ideal VBE0; this has been termed 'charge-pumping' [14],

[15]. The term 'soft' rectification means that the NPN transistor exhibits a modulated DC operating point, but the interfering noise is not enough to cause the device to switch off fully (that effect being termed 'hard' rectification). While power stage noise may certainly be enough to cause transistor switch-off, in this work only a 'soft' rectification effect is considered.

In terms of the low-pass filtering behavior of the sensor circuit, the following points can be considered:

1. The negative-going noise pulse is much more critical in generating a DC shift than the positive-going pulse. This is because a negative pulse causes the base-emitter voltage of the transistor to increase, driving it into a more active region, and having much more effect on the charge stored on the capacitor. In contrast, the base-emitter voltage will decrease for a positive-going pulse, making it less active, and having less effect on the capacitor charge. Because of this, the charge-pumping phenomenon will tend to push the generated base-emitter voltages lower, as shown in figure 4 (e).

2. Figure 4(d) shows the discharge-recover paths for negative-going noise pulses. When the noise pulse is induced in the circuit, the capacitor discharges through the transistor. The capacitor then recovers via the current source. The bias current source thus has two main effects in the circuit: (a) A higher magnitude means that the transconductance of the transistor will be higher, as it will be biased higher up its IC-VBE curve. This gives a lower 1/gm value, meaning the cut-off frequency of the transistor-capacitor LPF will be higher, and so noise will tend to pass through the circuit. (b) The capacitor will recover faster with a higher bias current. Both of these factors indicate that there is less chance of charge-pumping occurring for higher bias current values.

3. As the saturation current, IS, and gm values will vary between different transistors, choice of transistor can be important in reducing the charge-pumping phenomenon. This will be covered in Section V.

4. As already mentioned, smaller capacitor values can also be used to reduce the filtering effect, as the cut-off frequency will be higher. Figure 4(e) illustrates this effect, where the 33pF capacitor has time to recover fully in one noise period, but the 500pF capacitor cannot recover in time before another noise pulse is induced in the circuit.

5. The switching frequency of the power conversion circuit is also a factor in the charge-pumping effect i.e. for higher switching frequencies the capacitor has less time to recover between induced noise pulses.

Finally, the non-linear behavior of the error can now also be explained. From the analysis above, we have it that a higher bias current values result in a circuit which is more immune to noise. Because the ΔVBE method uses two different bias currents, the VBE generated using the lower switched bias current will be more affected by noise than the one generated using the higher bias current. Because of this asymmetry, and because ΔVBE = VBE2 - VBE1, there will be a corresponding non-linear (positive) increase in error (see figure 4(b)).

Figure 4. ΔVBE Error Mechanism

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III. SPICE MODEL

To simulate the error mechanism detailed in the previous section, a Spice model as shown in figure 5 (a) is created. The steps required are described in this section, using where necessary details and measurements from the power module in question.

A. Modelling the switching loop

The power stage switching loop is modeled using the simplifications described in [7]-[10]. First, the COSS value of the high-side FET is obtained by referring to the vendor data sheet. In this application, three parallel MOSFETS are used, resulting in a value of 2000pF. Next, an oscilloscope is used to probe the ringing at the switch node on the power module, and the resonant frequency, fres is measured as 64MHz (see figure 6). From this and the value of COSS, the loop inductance, LLOOP is calculated as:

𝐿𝐿𝑂𝑂𝑃 = 1

4𝜋2𝑓𝑟𝑒𝑠2 𝐶𝑂𝑆𝑆

(6)

This gives a loop inductance of 3.1nH; a value of 3nH is used in the model. Finally, the resistive term RLOSS is obtained using a trial-and-error approach in Spice. Using the values of LLOOP and COSS obtained above and exciting the simple RLC loop with a voltage pulse generator, the resistive loss term is adjusted until the switch node waveform in Spice is similar to the oscilloscope capture in figure 6(a). A value of 100mΩ was seen to be a good choice in this model. Finally, to complete the switching loop model, the pulse voltage source is replaced with a pulse current source to represent the switching action of the high-side FET.

B. Modelling the Inductive Coupling

Two steps are required to model the inductive coupling. First, an inductor is added to the NPN sensor circuit to model such factors as PCB trace and NPN/capacitor parasitic inductances. The value of this 'lumped' inductor is expected to be in the low nH range; for example, PCB traces have an approximate inductance of 1nH/mm, while bond wires/capacitor connection inductances will also generally be in the sub 1nH range [16]. To simplify matters, however, a value of 3nH is chosen, as it directly matches the switching loop inductance calculated above.

Next, the mutual inductance coupling coefficient parameter of Spice is used to model the coupling between the power stage loop inductance and the NPN circuit. This is a unit-less parameter termed 'k', and when both loop inductances are equal, the mutual inductance, LM, between the two circuits can be defined simply as:

𝐿𝑀 = 𝑘𝐿1 (7)

where L1 is the value of the equal loop inductances. So, for example, a coupling coefficient of k = 0.05 gives a mutual inductance of 150pH for two loop inductances of equal value 3nH.

C. Modelling the Controller Temperature Sense Block

The final step is to model the controller temperature sense block. A single DC current source, rather than a switched current source, is used to generate the bias for the NPN transistor. A particular simulation is then run separately for each bias current (e.g. 5uA and 100uA) to obtain VBE1 and VBE2 figures, with the difference giving the ΔVBE figure. The

Figure 5. (a) Spice model. (b) Charge-pumping effect in model

Figure 6. Switch node voltage (measured and simulated)

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controller block model also includes an internal low-pass filter, as well as a 1GΩ resistor to model the input impedance of an internal amplification circuit. These extra components have no bearing on the temperature reporting error, the DC shift having already taken place external to the block. Finally, the transistor and capacitor are represented by their usual components. For the transistor, Spice models can be obtained from vendor websites as normal.

Figure 5 (b) shows an example simulation result where the DC shift of the base-emitter voltage is plotted for DC-DC convertor load currents of 0A, 10A, 20A and 30A. This plot confirms the charge-pumping hypothesis described in section II.

IV. EXPERIMENTAL RESULTS USING POWER MODULE

In this section, experimental results collected using the power module which exhibited the error are presented, and they are compared to simulation results obtained using the model described above. The test set-up is shown in figure 7; note that the transistor used is the Diodes Inc ZXTN26020DMF. The power module is configured to regulate to 1.0V, with the line voltage set to 12V, and a thermocouple is used to monitor the temperature of the power module. A LabVIEW test program is then used to vary DC-DC converter load current, switching frequency and NPN bias currents, and the equivalent ΔVBE temperature (calculated by FW) is read back from the controller. The deviation of the ΔVBE temperature from the thermocouple measurement is then plotted. Identical test scenarios are simulated using the Spice software, Simetrix [17]. Note that in the model, a coupling coefficient parameter ('k') of 0.05 is used, simply because it leads to results which are somewhat similar to measurement. One of the limitations of the model is that it is extremely difficult to calculate a value that exactly represents the real coupling on a PCB, and so this simple approach must be used. This also means that the model only produces results which predict the general behavior of the circuit, rather than providing data which directly matches measured results. Note

also that the simulation returns results in voltage terms, which must be converted to ΔVBE temperature using the following equation:

𝑇 = 𝑞 .∆𝑉𝐵𝐸

𝑘 .𝑙𝑛(𝐼𝐶2 𝐼𝐶1) (8)

From the discussion in Section II, the error magnitude is expected to increase in line with the following factors: (a) noise pulse magnitude, which is proportional to load current; (b) Noise pulse frequency, i.e. regulator switching frequency; (c) Lower NPN bias currents, or different transistors; (d) Higher noise capacitor values. The results of both measurement and simulation presented in this section confirm these factors. Figure 8 shows the modeled and measured results where load current is increased for different switching frequencies, with both plots exhibiting the non-linear temperature behavior as expected. Also, it can be seen that the error increases as switching frequency is increased.

Next, figure 9 shows the behavior when different switched-bias current combinations are used. Note that the controller has an option of using three different switched-bias combinations: 5uA/100uA; 10uA/200uA; 20uA/400uA (the ratio of 20 is retained for each). The temperature deviation is plotted here for each option (the DC-DC settings are fsw = 500kHz, VIN = 12V, VO = 1.0V). The theory predicts that higher bias-currents are more immune to injected noise, and this is confirmed in both measurement and modeling. Note

Figure 7. Test set-up using original power module

Figure 8. ΔVBE Temperature plotted against load current.

(a) Simulation (b) Measurement

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that the related investigation of transistor type will be discussed in Section V.

An investigation of capacitor values leads to somewhat more complex findings. Figure 10 compares the temperature error for a range of X7R and C0G/NPO capacitors, alongside simulation results. The DC-DC settings are fsw = 500kHz, VIN = 12V, VO = 1.0V, Load = 20A. Each capacitor type is chosen from a specific vendor range to improve consistency of results. As predicted by theory, the ΔVBE error increases as capacitor value is increased. However, the measured results exhibit multiple peaks, perhaps indicating complex resonant interactions between the PCB geometry and hidden parasitic elements such as capacitor ESR/ESL. This plot also indicates that the performance with C0G/NPO capacitors starts to degrade earlier than with X7R types. The results are somewhat misleading, however- figure 11 compares the results obtained for four different 100pF capacitors (X7R Type1 and C0G Type 3 correspond to the capacitors used in the figure 10), and a different error is exhibited for each capacitor. The difference in results can again possibly be explained by complex resonant interactions which are dependent on capacitor parasitics, and the Spice model is not sophisticated enough to account for higher order effects.

This leads to some uncertainty as to the best choice of capacitor. Removing the capacitor still leads to an error as

power stage noise will still affect the ΔVBE signal (this was verified in this work, as an error of 10°C still existed when the capacitor was removed). The aim then is to choose a value of capacitor which offers some noise immunity without causing a DC shift via the charge-pumping effect. From the measurements carried out, the optimal choice appears to be in the range of 50pF-80pF; this should ensure that some noise filtering is still achieved, yet charge-pumping will not occur.

V. EFFECT OF TRANSISTOR TYPE

In section II, it was predicted that a higher transconductance, gm, would result in a higher noise immunity in this application. A simplified equation for transconductance was also given as:

𝑔𝑚 = 𝐼𝑆

𝑉𝑇𝑒𝑉𝐵𝐸/𝑉𝑇 (9)

The values of IS and VBE will vary according to transistor type, with VBE also being dependent on the applied bias current. As the cut-off frequency of the low-pass filter created by the NPN/noise capacitor combination is related to gm, the choice of transistor will have a bearing on the noise immunity of the circuit. However, because of the unusual footprint (DFN1411) of the transistor used on the original power module, it was impossible to interchange transistors to investigate this effect. Instead, a simple noise injection test

Figure 10. Effect of capacitor value on ΔVBE Error.

Figure 11. Comparison of four 100pF capacitors.

0

20

40

60

80

100

120

140

160

1 10 100 1000

ΔVBE

Temp.

Error

(°C)

Noise Capacitor (pF)

Effect of Capacitor on ΔVBE Error

Model Data

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20.5

82

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60

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80

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X7R Type 1 C0G Type 1 C0G Type 2 C0G Type 3

ΔVBE

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(°C)

Comparison of Four 100pF Capacitors

X7R Type 1

C0G Type 1

C0G Type 2

C0G Type 3

Figure 9. ΔVBE Temperature plotted Vs load current for different

ΔVBE switched-bias currents. (a) Simulation (b) Measurement

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circuit as shown in figure 12 was used to investigate the charge-pumping behavior exhibited by different transistors. An AWG is used to inject a pulse of very narrow width (20ns) on the emitter of the transistor under test. The frequency and magnitude of the pulse is varied to give a noise profile similar to that observed on the real application (i.e. frequencies of 250kHz to 1000kHz, and magnitudes of 50mV to 200mV), and the VBE deviation for various bias currents is measured. Also, only a single negative-going pulse is used, as this noise pulse has most effect on the charge-pumping mechanism, as explained in Section II.

The oscilloscope plot in figure 13 illustrates the charge- pumping effect for the MMBT3904 transistor in conjunction with a 470pF noise capacitor. The NPN bias current is 5uA, and the noise pulse magnitude is -150mV, with a frequency of 500kHz. For this transistor, the base-emitter voltage shifts about 23mV lower than the ideal. This data is extracted from the oscilloscope, and also plotted (using Matlab) in figure 14, along with the results for the ZXTN25012 and BC848C transistors. A basic filtering operation is also carried out in Matlab to show more clearly the difference in charge-pumping for each transistor; this plot clearly indicates that different transistors are affected differently by injected noise.

Finally, figure 15 compares the ΔVBE results for 11 different transistors. The noise conditions are as above, but this time the VBE error is measured for both 5uA and 100uA NPN bias currents, and the ΔVBE error is calculated and converted to an equivalent temperature error. As can be seen, the temperature error is lowest for the PBSS4023NT. At 15°C

this is still quite high (although the noise pulse amplitude is also high in this case), but it improves on the worst case by a factor of 5. In practical terms, this particular transistor is relatively expensive, and so cheaper types such as the BC850 or BCW33 may be a better option in mass production applications, as they still yield improved noise performance at a lower cost.

One final important point which may not be obvious needs to be made regarding these results. The reason that the noise performance improves for these three transistors (PBSS4032NT, BC850C and BCW33) is that little or no charge-pumping is taking place in the circuit, and so a meaningful DC shift does not occur (although the noise still causes some error). If charge-pumping is not taking place, then reducing the noise capacitor or increasing the NPN bias currents has very little effect on the ΔVBE error. For example, figure 16 displays the results for the PBSS4032NT transistor for a range of bias currents, showing a minimal change in error (all other test conditions are identical to above). In this scenario, the only option available to improve the noise

Figure 12. Test circuit to investigate the noise susceptibility of

different transistors

Figure 13. Oscilloscope plot showing charge-pumping for

MMBT3904 transistor and 470pF capacitor. Bias current is 5uA.

Noise characteristics: Peak = -150mV, width = 20ns, frequency =

500kHz. Top trace = noise pulse; bottom trace = capacitor voltage

Figure 14. Charge-pumping effect on three NPN transistors for

identical bias and noise conditions.

Figure 15. ΔVBE error for different transistors. Bias currents are 5uA

and 100uA. Noise characteristics: Peak = -150mV, width = 20ns,

frequency = 500kHz.

66 6575

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ΔVBE

Temp

Error

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ΔVBE Temperature Error for Different Transistors

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immunity of the circuit is sensible PCB layout i.e. the ΔVBE circuit must be placed in as quiet a location as possible while still providing useful thermal information.

VI. CONCLUSION

This paper has discussed the noise susceptibility of precision ΔVBE temperature sense circuits when used in power conversion circuits. It has been proposed that power-stage noise is inductively coupled to the ΔVBE circuit, leading to a rectification/charge-pumping effect which ultimately causes a DC shift of the ΔVBE signal. A Spice model based on this hypothesis has been presented, and experimental results are seen to be in agreement with simulation. The work has revealed several important design guidelines which can significantly improve the accuracy of ΔVBE temperature sense circuits when exposed to high levels of electromagnetic interference, and these are listed below:

1. Sensor location is critical: the ΔVBE circuit should be placed as far away from the switching node/loop as possible, while still providing useful thermal information.

2. To improve the noise immunity of the circuit, analog designers should use relatively high switched-bias currents in generating the ΔVBE signal.

3. Noise capacitor values in the range of about 50pF-80pF are recommended, as some noise filtering is still provided, but there is less chance that a rectification/charge-pumping effect will occur.

4. Transistor choice is important. This work suggests that transistors such as the PBSS4032NT, BCW33 or BC850C are a good choice.

REFERENCES

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[3] D. Rodriguez, S. Chun, R. Mandrekar, and D. Dreps, "Switching regulator noise coupled onto high speed differential links," IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp 203–206, October 2011.

[4] M. A. P. Pertijs and J. H. Huijsing. Precision Temperature Sensors in CMOS Technology. Springer, Dordrecht, 2010.

[5] T.C. Verster. p–n junction as an ultralinear calculable thermometer. Electronics Letters, 4(9):175–176, May 1968.

[6] A. T. Mozipo, "Analysis of a current sensing and reporting tolerance in an inductor DCR sense topology," IEEE Applied Power Electronics Conference and Exposition (APEC), pp 1502–1506, March 2011.

[7] F. Centola Cheung-Wei Lam R. Steinfeld. K. Kam, D. Pommerenke. EMC guideline for synchronous buck converter design. IEEE International Symposium on Electromagnetic Compatibility, pages 47–52, August 2009.

[8] D. Pommerenke. K. Kam. EMI analysis methods for synchronous buck converter EMI root cause analysis. IEEE International Symposium on Electromagnetic Compatibility, pages 1–7, August 2008.

[9] K. Kam F. Centrola Cheung-Wei Lam A. Bhargava, D. Pommerenke. DC-DC buck converter EMI reduction using PCB layout modification. IEEE Transactions on Electromagnetic Compatibility, 53:806–813, August 2011.

[10] D. Zhe Li; Pommerenke. EMI specifics of synchronous DC-DC buck converters. IEEE Symposium on Electromagnetic Compatibility, 3:711–714, 2005.

[11] Martin Graham Howard Johnson. High Speed Digital Design- A Handbook of Black Magic. Prentice Hall, 1993.

[12] Jean-Michel Redoute and Michiel Steyaert. EMC of Analog Integrated Circuits. Springer, 2010.

[13] Paul R. Gray; Paul J. Hurst; Stephen H. Lewis; Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley and Sons, Inc., 2010.

[14] Jean-Michel Redoute; Michiel Steyaert. Current mirror structure insensitive to conducted EMI. IEE Electronic Letters, 41:1145–1146, October 2005.

[15] A. Wieers and H. Casier. Methodology and case study for high immunity automotive design. Proceedings of the 15th Workshop on the Advances in Analog Circuit Design, Maastricht, The Netherlands, April 2006.

[16] Eric Bogatin. Signal and Power Integrity - Simplified. Pearson Education, Inc., 2004.

[17] "SIMetrix/SIMPLIS Advanced Power System Simulation, Release 6.00c". http://www.simetrix.co.uk (Accessed May 2013).

Figure 16. ΔVBE temperature error for the PBSS4032NT

transistor for a range of bias currents. If charge-pumping is not

taking place in the circuit, then using higher bias currents has

little effect on the error.

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