A Flexible Biphasic Pulse Generating and Accurate Charge BalancingStimulator with a 1μW Neural Recording Amplifier

Hosung Chun, Omid Kavehei, Nhan Tran and Stan SkafidasDepartment of Electrical and Electronic Engineering, University of Melbourne

Melbourne, AustraliaEmail: hosung.chun@unimelb.edu.au

Abstract— In this paper, we present a flexible biphasic pulsegenerating and accurate charge balancing stimulator with a1μW neural recording amplifier. To achieve accurate chargebalance, the stimulator is implemented using a dynamic currentcopying technique. It can generate a biphasic current pulse withan anodic scaling feature. To reduce power consumption, therecording amplifier is implemented to operate with 1V, whilethe stimulator works with 3V supply. They are implementedusing a 65nm CMOS process. Simulation results show chargebalance of less than 2% error in current pulses. The recordingamplifier has an input referred noise of 4.5μVrms and passbandfrom 1.5Hz to 5KHz with the power consumption of 1μW.

I. INTRODUCTION

Advances in technology have brought hope for impairedindividuals to recover their lost function with the help ofimplantable neuro-prosthetic devices. Cochlear implant [1],vision prosthesis [2], pace-maker [3] are good examples.Fig.1 displays a general implantable multi-channel neuralsystem. The neural system consists of a power and datarecovery circuit, stimulator/recording channels, ADCs, digi-tal controllers and a reverse telemetry. Normally, power anddata are inductively coupled to the implanting neural system,minimising an infection risk. To induce a desired neurolog-ical response, the stimulator applies electrical stimuli on animpaired tissue. So far, the biphasic current pulse has been apopular stimulus due to its charge balancing capability [4].Implanting neural systems often contain a neural recordingfunction to monitor the neural activity of neurons duringstimulation. The recording amplifier observes the neuralactivity, which helps understanding the physiological behav-ior of neurons and developing a more efficient stimulationstrategy. The captured neural signals are converted to digitalformat by ADC and sent externally through the reversetelemetry.One of the most important concerns while using such neuro-prosthetic devices is to ensure safety for chronic stimulation.This necessitates an accurate charge balance capability [5]and a low power consumption [6] from implantable pros-thetic devices. Though many state-of-arts, achieving accuratecharge balance, are reported in [4], [7] and [8], they allcome with extra power and area penalty. Even if [5] achievesaccurate charge balance in a simple and compact mannerby utilising a dynamic current copying, it only generates asymmetric biphasic pulse.Neural signals typically reside in the frequency range ofsub hertz to a few kilo hertz with their amplitudes varying

ADC

GlobalDigitalControl

Power/DataRecovery

Bias

Sstim

Stimulator

RecordingAmplifier

LocalDigitalControl

Srec

Electrode2

ElectrodeNCH1

CH2

CHN

Electrode1ReverseTelemetry

Stimulator & RecordingChannel

Implantable Multi-ChannelNeural System

Fig. 1. A General Implantable Multi-Channel Neural System

between a few μV and several mV [9]. Therefore, therecording amplifier is required to have a low input-referrednoise without consuming much power [10], [11]. But thenoise performance is a trade-off with power consumption.In general, the power consumption of implantable prostheticdevices is limited by several tens of mW, depending on thedimension of devices [6].In this work, to achieve accurate charge balance, the stimu-lator is implemented using the dynamic current copying [5]but with an enhanced feature of generating flexible currentpulses. To reduce power consumption, the recording ampli-fier is implemented to operate under 1V, while the stimulatorworks under 3V supply. They are implemented using a 65nmCMOS process. Simulation results show charge balance ofless than 2% error in stimulus pulses. The recording amplifierhas an input referred noise of 4.5μVrms and passband from1.5Hz to 5KHz with the power consumption of 1μW.

II. STIMULATOR

In electrical stimulation using current pulses, in one phase,a stimulator delivers charge to a tissue to cause a desiredneurological response, while it recovers charge from thetissue in the following phase. To prevent DC current flowinginto the tissue, it is mandatory that the charge deliveredin one phase should be fully recovered in the followingphase. Though various forms of charge monitoring andbalancing circuits have been reported in [4], [7] and [8], theirextra power and area requirements make their applicationdifficult for implantable multi-channel prosthetic devices. Adynamic current copying stimulator [5] achieves accuratecharge balance in a simple and compact manner, though itlacks of versatility.The stimulator in this work is implemented using the dy-namic current copying to achieve accurate charge balance. It

978-1-4673-5762-3/13/$31.00 ©2013 IEEE 1885

is enhanced with a feature of generating more flexible formof current pulses.

A. Dynamic Current Copying Stimulator Front-End

The schematic of the stimulator with the dynamic currentcopying is illustrated in Fig.2. The stimulator consists of acurrent source driver (M6-9, C1, MC2 and OTA2), a currentsink driver (M0-5, DAC, MC1 and OTA1) and shortingswitches. A gain enhanced cascode structure is utilised toincrease output impedances of the current drivers. A singlestage OTA [12] is utilised for OTA1 (pmos input pair) andOTA2 (nmos input pair). They are designed to consume lessthan 50μW each and their settling time is less than 1μs. VBNand VBP are 0.3V above the ground and below the supplyvoltage (3V), respectively, setting the voltage headroom ofcurrent drivers. The DAC has a 4-bit resolution with 1 LSBcurrent of 0.5μA. The DAC current is copied to the currentsink driver, which is also DAC (binary weighted structure)with a 5-bit resolution. With this architecture, the stimulatorcan provide a wide range of stimulation current with a fineresolution. Basically, it operates in 4 sequences for singlestimulation. During Φ1 (sampling phase), the stimulationcurrent is established by connecting the current sink andsource together. The current source driver (M6-9) samplesits gate-source voltage on C1. S1-5 are selectively closed,based on the stimulation current levels. In Φ2 (cathodicphase), the cathodic current conducts from VDD to the currentsink driver via the return and active electrodes. Anodiccurrent flows from the current source to GND via the activeand return electrodes. During Φ4 (shorting), the electrodesare connected to a shorting potential through the shortingswitches.The minimum required time for the sampling phase (Φ1)heavily depends on the settling time of OTA1 and OTA2. Toreduce a channel charge injection to C1, a transmission gatewith a dummy structure is used. Also, a large capacitor (6pFmimcap) is used for C1.

B. Flexible Current Pulses: Anodic Scaling

To generate more flexible current pulses, the current sourcedriver is implemented with 4 identical transistors, such asM6-9. By controlling switching sequence of S6-9, anodicscaling can be done in two different ways; an ascending(current copying) and a descending (current splitting) order.In the ascending manner, the anodic current is scaled up witha factor of 1, 2 and 4, comparing with the cathodic current.During Φ1 (sampling phase), S6 is only on and its gate-sourcevoltage to conduct the cathodic current is sampled on C1.Then, in Φ3 (anodic phase), depending on the scaling factor,S7-8 are selectively on. For example, if the anodic currentis twice of the cathodic current (scaling factor 2), S6 andS7 are on during Φ3. In this case, to ensure charge balance,the duration of the anodic phase should be set to the half ofthe one of the cathodic phase. In the ascending manner, thisstimulator can generate current pulses of cathodic vs anodiccurrent ratio of 1:1 (S6 on), 1:2 (S6-7 on) and 1:4 (S6-9 on).In the descending manner, the anodic current is scaled down

OTA1

OTA2

DAC

1 x

VDD

2 x 4 x 8 x 16 x

VBN

GND

VBP

M1 M2 M3 M4 M5M0

VDD=3V

MC1

MC2

ReturnElectrode

C1

ActiveElectrode

Tissue-Interface

Vshort

M6 M7 M8 M9

Vshort

S1 S5

S8S7S6

S4S3

S9

S2

1 x 1 x 1 x

Φ1

Φ1&Φ2

Φ2

Φ3

Φ4Φ4

Φ1&Φ3

Φ1

Φ2

Φ3

Φ4

Fig. 2. Schematic of the Stimulator

with a factor of 1, 0.5 and 0.25 in comparison with thecathodic current. During Φ1 (sampling phase), S6-9 are all onand the sum of M6-9 (the anodic current) are the same as thecathodic current drawn by the current sink driver. The anodiccurrent can be set to a quarter or a half of the cathodic currentby turning on 1 or 2 transistors from M6-9, respectively. If2 transistors (M6-7) are on during Φ3, the anodic currentbecomes a half of the cathodic current. In this case, to ensurecharge balance, the duration of the anodic phase has to bedouble of the cathodic phase. If 4 transistors (M6-9) are on,the stimulator generates a biphasic current pulse with equalamplitude in the cathodic and anodic phases. Therefore, thisstimulator can generate current pulses of cathodic vs anodiccurrent ratio of 1:1 (S6-9 on), 1:0.5 (S6-7 on) and 1:0.25 (S6on).

III. NEURAL RECORDING AMPLIFIER

A. Generic Architecture

Fig.3 displays the implemented fully differential neuralrecording amplifier. MP1-P4 are utilised to implement a largefeedback resistor, as MOS-bipolar pseudo-resistors. Eachtransistor is sized 2μm x 2μm. Simulation shows that theirvalues (Rpseudo) go over several hundreds GΩ. The closedloop gain of the recording amplifier is Cin/Cf. It is designedto be 40dB by choosing Cin=5pF and Cf=50fF. The outputof the recording amplifier is to drive 1pF load at the inputof ADC. MIMCAP is utilised for Cin, Cf and CLOAD. Thehigh-pass filter (HPF) cutoff frequency is determined by1/2πRpseudoRf. The low-pass filter (LPF) cutoff frequencyis related to the input transistor’s transconductance and theload capacitance.

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Cin

Cin

Cf

Cf

CLOAD VOUT

MeasuringElectrode

ReferenceElectrode

VIN

MP3 MP4

MP2MP1

TissueLNA

Fig. 3. Schematic of Neural Recording Amplifier, where LNA is low-noiseamplifier

B. Noise Analysis

The overall noise of low-noise amplifier (LNA) in Fig.4consists of a thermal noise component and a flicker (1/f)noise component. The noise sources were modeled as voltagesources in series with the input. Then, the input referred noiseof the LNA is given as

V 2in = 2 ×

[4kT

gm1

(23

) (1 +

2gm3

gm1+

gm7

gm1

)]+ 2 × 1

f×

[KP

CoxW1L1+

2KN

CoxW3L3

(gm3

gm1

)2

+KP

CoxW7L7

(gm7

gm1

)2]

(1)where k is Boltzmann’s constant, T is the temperature inKelvin, gm is transconductance, Cox is the metal oxide ca-pacitance, KP and KN are the 1/f noise coefficients of PMOSand NMOS transistors in a given process, respectively. Thefirst part of (1) is the thermal noise contribution and thesecond part is due to 1/f noise. From (1), it is clear thatincreasing gm1 helps improving overall noise performance ofthe amplifier. Flicker noise, or 1/f noise, is a major concern inlow frequency band signal. To minimise the effect of flickernoise, PMOS differential pair is utilised as an input device.As the large gate area helps reducing flicker noise, the devicesize of the low noise amplifier (LNA) in Fig.4 is critical forachieving low noise at low current level. To reduce powerconsumption, the LNA is designed to operate with 1V powersupply. Total power consumption of LNA is 1μW, includingthe tcommon mode feedback circuitry.

IV. SIMULATION RESULTS

Simulations are performed with the following base-lineparameters; 1) stimulation period: 1ms, 2) Φ1: 50μs, 3) Φ2:100μs, 4) Φ3: 100μs and 5) Φ4: 0.72ms. A minimum timefor Φ1 is 10μs, which is determined by the settling time ofOTAs. Inter-phase delay is set to 10μs. The duration of theΦ3 is inversely proportional to the anodic scaling factor. Fig.5

M7

M3M5M6

VDD = 1V

M4

M1 M2

M0

M8

VIN- VIN+

VB1

GND

VOUT-

M9

M11 M12

M10

VOUT+

VB2

VB3

VB2

VB3

VB4

VOUT-VOUT+

VCM

M13 M16

M17 M18

M14 M15

M19 M20

Fig. 4. Fully Differential LNA (low-noise amplifier) including commonmode feedback

TABLE ILNA DEVICE DIMENSION

Transistor W/L (μm)M1-2 200/1M3-6 3/60M7-8 3/30M9-12 20/1M13-16 20/1M17-18 1/15M19-20 3/15

shows the generated current pulses with different anodicscaling factors; 0.25, 0.5, 1, 2 and 4 in order. In Fig.5, thecathodic phase starts first, followed by the anodic phase. Thestimulator can also be configured to have the anodic phasestart first, shown in Fig.6. The matching accuracy of anodicscaling is summarised in Table. II. The stimulator achievesthe best matching accuracy (less than 0.1%) when the scalingfactor is set to 1, while it shows the worst matching (1.8%)with the scaling factor of 4. This is due to CMOS processvariation effect on the threshold voltages of M6-9. However,this is still acceptable level to prevent DC current flowinginto tissue.Fig.7 displays the frequency response of the LNA. Its gain is40dB and its passband is from 1.5Hz to 5.02KHz. The inputreferred noise is 4.5μVrms. Corner simulation shows that theHPF is 3.8HZ at FF and 0.8Hz at SS. The characteristics ofLNA is summarised in Table III.

V. CONCLUSION

In this paper, we present a flexible biphasic pulse gener-ating and accurate charge balancing stimulator with a 1μWneural recording amplifier. The stimulator is implementedusing the dynamic current copying with an enhanced featureof generating flexible current pulses. To reduce power con-sumption, the recording amplifier is implemented to operateunder 1V, while the stimulator works under 3V supply. Theyare implemented using a 65nm CMOS process. Simulationresults show charge balance of less than 2% error in stimuluspulses. The recording amplifier has an input referred noiseof 4.5μVrms and passband from 1.5Hz to 5KHz with thepower consumption of 1μW.

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TABLE IIANODIC SCALING SIMULATION RESULTS

Scaling Factor IAnodic ICathodic ΔQ % error4 249.5μA 61.3μA 107pC < 1.8%2 124.4μA 61.3μA 90pC < 1.5%1 61.2μA 61.3μA 9pC < 0.1%0.5 30.3μA 61.3μA 70pC < 1.2%0.25 15.2μA 61.3μA 50pC < 0.9%

TABLE IIINEURAL RECORDING AMPLIFIER PERFORMANCE SUMMARY

Supply 1VTechnology 65nmPower consumption 1μWGain 40dBBandwidth 1.5Hz-5.02KHzICMR 0.2V-0.75Ouput Swing 0.65VppInput referred Noise 4.5μVrmsCMRR (1Hz-5KHz) > 45dBPSRR (1Hz-5KHz) > 43dB

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