A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs

Ward S. Titus, John G. Kenney

Analog Devices, Somerset, NJ, 08873, USA

Abstract — A DCO is realized in 0.13μ CMOS using 4

cores for a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for an all digital D/PLL CDR circuit. The DCO is novel in that it can track more than a 130 degree C temperature variation while the CDR maintains an error free lock to data. Each core is directly coupled to a div/2 to produce I/Q signals that a 4:1 MUX combines into a single set of 2.8 to 5.8 GHz quadrature outputs to drive the sine interpolator of the CDR. Locked to maximum data rms jitter, integrated from 1 kHz to 1 GHz is 299 fs @ 9.953 Gb/s (Sonet OC-192) from a DCO phase noise of -116 dBc/Hz at 1 MHz offset. The kDCO gain is 190 ppm/bit with less than 2:1 variation over the full BW. The combined DCO, divide by 2 and MUX current is 14 mA to 37 mA on a 1.2V regulated supply at 25C.

Index Terms — CMOS, DCO, DPLL, varactors, VCO.

I. INTRODUCTION

A dual loop Clock Data Recovery (CDR) architecture is shown to offer the benefit of simultaneous low jitter transfer and high jitter tolerance while delivering zero jitter peaking desired for Sonet systems [1-3]. A very low loop bandwidth (BW) for the temperature tracking loop is then required to avoid upsetting the low jitter peaking of the architecture which usually requires a large off-chip filter cap in traditional analog loop implementations such as the 68nF cap in [2]. An all digital implementation of the dual loop architecture shown in Fig 1 could replace this off-chip cap with a digital integrator saving board space and external components.

Fig. 1. Digital Dual Loop CDR Block Diagram

For this all digital approach, a digitally controlled oscillator (DCO) that can continuously track temperature variations in oscillator frequency while locked to data is required. DCOs with GHz carrier frequencies are typically developed for narrow bandwidth wireless applications such as TDMA that don’t require continuous operation over temperature since they can be recalibrated for each

packet of data at a rate well below thermal time constants [4]. In this work, a DCO with 6 GHz BW, 11.5 GHz maximum frequency and a -45C to 85C temperature tracking range is developed to extend the CDRs in [1,2] to OC 192 rate using an all digital loop.

II. DESIGN

The DCO uses 4 cores, each directly coupled to its own divide by 2 and then multiplexed to produce quadrature differential clocks for the CDR as shown in Fig 2. A tunable low pass filter at the outputs helps re-form the sinusoidal inputs to the subsequent sine interpolator phase shifter that creates the delayed clock for the CDR data sampler / phase detector. Only 1 core is operated at a time with the other cores and their corresponding dividers powered down for isolation and to save DC power.

Fig. 2. DCO Block Diagram Each DCO core has 3 digitally controlled varactor

tuning blocks as shown in Fig 3. All of the varactors in the DCO are nMOS devices set to either logic LO or logic HI voltages.

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978-1-4244-8292-4/11/$26.00 ©2011 IEEE

The largest bandwidth tuning control is an 8 bit binary weighted array of process, rate tuning bits with 30% tuning BW which in conjunction with the 4 core selection provides 10 bit binary (1024 state) 6 GHz BW frequency control of the DCO. These binary bits are held constant after initial CDR acquisition to the data rate.

The second digital tuning block is a 256 element array of latched bits shown in Fig 4 with 3% tuning BW to track the 104 ppm/degC measured frequency variation with temperature and pull-in to lock. The built in array memory retains the frequency state while only 1 bit at a time is changed to minimize frequency glitches to less than 1 LSB during normal operation. The 16 row, 16 column addressing to this array reduces the number of wires to 33 including data which reduces capacitive parasitics and enables 11 GHz operation. At startup before data recovery has begun, glitches are not important so a fast setting to mid code (128) is enabled by partitioning the data wire into two regions, pulling all address wires HI and setting 1/2 region data wire HI, the other LO. Incorporating the latch into the array permits such operation where the simple relational logic used in [5] would not.

Fig. 3. DCO Core Schematic Fig. 4. Temperature Drift Array Latched Bit Schematic

A strobe signal is logically AND-ed with all address bits to precisely time the 1 bit transition in conjunction with the fine PLL control.

Finally, each core has a third array of 32 individually wired bits with 0.4% BW for the PLL fine frequency control at a 700 MHz rate. By design these fine tune bits have the same kDCO gain as the latched array bits, 190 ppm nominal measurement and are scaled between DCO cores for a 2:1 variation in kDCO gain over the full BW for tight control of the CDR jitter transfer bandwidth.

A thick top metal, 8 level metallization process is used to fabricate high Q inductors in the top most 3μ thick metal, high above the Si substrate for lowest parasitic capacitance. The inductors are less than 1 turn with no underpass for high Q, very small size and compact layout, 0.07 to 0.11nH inductance, so a large tuning bandwidth is obtained from the digitally controlled capacitance.

The DCO also features an automatic leveling control loop (ALC) with programmable bandwidth having a fast acquisition mode with 20ns time constant and a normal mode with 1000x longer time constant for low DCO phase noise. The ALC amplitude level is also 4 bit programmable and nominally sets a low 1.2Vppd nominal tank swing to maintain a desirable compromise between the competing goals of low kVDD for low regulator contribution to random JGEN and good phase noise for a low DCO contribution to random JGEN. The ALC control also maintains reliable divider operation.

III. MEASUREMENTS

The DCO is successfully integrated into an anyrate all digital loop CDR that demonstrates Sonet OC-192 (9.953 Gb/s) compliance with a measured 1.5 MHz jitter transfer BW and 450 fs jitter generation for PRBS31. DCO measurements are made from the full CDR chip in a 24 pin LFCSP package using its differential divide by 2 clock outputs. The measured DCO divide by 2 frequency response is shown in Fig 5 for the 4 cores as the coarse 8 bit tuning word is swept over each of its 256 states, 10 bits total. Overlaps between cores guarantee no gaps in tunable frequency for more than an octave bandwidth. The measured kDCO of the temperature drift latched array is shown in Fig 6, varying less than 2:1 over all cores and coarse tuning word values that set the minimum to maximum DCO frequency. As the fine tune PLL varactors have the same size and kDCO value, this ΔkDCO is the variation of the DCO gain seen by the PLL and so contributes that variation to the dual loop D/PLL CDR’s jitter transfer BW (JtranBW) whose variation we desire to minimize.

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Fig. 5. Measured DCO core divide by 2 frequency tuning vs. 10 bit coarse tuning word

Fig 6. Measured fine kDCO vs. 8 bit coarse tuning word

Operation of the temperature drift array can be seen by recording the variation of its 8 bit word while the CDR is locked to data and temperature is then varied as shown in Fig 7. In this measurement, the CDR is locked at 25C and temperature is then reduced slowly for thermal settling in 1 degree steps to -45C, then raised in 1 degree steps to 85C and finally reduced back to 25C, forming a complete loop. The CDR maintains an errorless lock to data for the 18 hour measurement time. In the CDR application, the DCO will need to track changes in temperature for years of operation. Only 40% of the 256 latched array codes are used to track the 130C range, enabling the DCO to startup at any temperature within that range with the latched array set to mid code and still have sufficient range to track lower or higher temperatures.

Open loop DCO phase noise on the divide by 2 output signal is shown in Fig 8 at a 4.98 GHz div/2 frequency for a 9.95 GHz core frequency. The corresponding closed loop phase noise when the CDR is locked to OC-192 maximum 0101 data is shown in Fig 9 for a 1 MHz

JtranBW. The -116 dBc/Hz open loop phase noise at 1 MHz offset is sufficiently low for the 1 kHz to 1 GHz integrated closed loop rms jitter to be 299fs, well below Sonet OC-192 requirements of 1ps. The open loop phase noise varies from -122 dBc/Hz for the lowest core, lowest frequency to -114 dBc/Hz for the highest core, highest frequency. The closed loop 50 kHz to 80 MHz rms jitter varies from 2 to 3 mUIrms where a UI is the unit interval or period of the data rate. So 299fs is 2.98 mUIrms at 9.953Gb/s OC-192.

Fig. 7. Measured DCO 8 bit temperature tuning word vs. temperature while locked to 6.62 Gb/s data Fig. 8. Measured free running phase noise at 9.95 GHz core

Fig 9. Measured 9.953 Gb/s locked phase noise and rms jitter

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Operation of the ALC leveling loop is seen from the variation of the combined DCO, divider and MUX current vs. the 10 bit core, coarse tune word in Fig 10. The ALC varies the current to maintain a 1.2Vpp differential tank swing for each core as the switched varactors vary tank Q. Fig. 10. Measured DCO/Div/Mux current vs. 10 bit coarse tuning word The 4 core DCO with dividers, 4:1 MUX and ALC circuitry occupies less than ¼ of the 2 x 2 mm CDR chip as shown in Fig 11. An on-chip 1.2V regulator also occupies this space. Its power supply rejection prevents low frequency supply noise that is multiplied by the DCO’s kVDD from degrading jitter Fig 11. DCO microphotograph

IV. CONCLUSION

A DCO with 6 GHz BW, 11.5 GHz maximum frequency, <2:1 ΔkDCO gain variation, 190 ppm/bit kDCO and -45C to 85C temperature tracking range is presented that extends an analog any rate, OC-48 maximum rate CDR to OC-192 rates using an all digital

loop control. Rms jitter integrated from 1 kHz to 1 GHz is 299 fs at 9.953 Gb/s achieved from a -116 dBc/Hz phase noise at 1 MHz offset. A performance summary is in Table I.

TABLE I PERFORMANCE SUMMARY

4 core DCO with divide by 2 and 4:1 MUXTechnology 0.13μ CMOS, 3μ met8Regulated Supply Voltage 1.2V Frequency 5.6 – 11.5 GHzBits of Digital Tuning 4 cores

8 binary bits coarse 256 states temperature 32 states fine (PLL)

DCO, Div, MUX current 14 mA to 37 mARMS Jitter * 299 fs at 9.953 Gb/sPhase Noise, 1 MHz offset -116 dBc/Hz at 9.95 GHz/2

-122 dBc/Hz at Fmin -114 dBc/Hz at Fmax

Temperature Range -45 to 85C using 40% range

Fine kDCO 190 ppm/bit Fine ΔkDCO < 2:1 * integrated 1 KHz to 1 GHz, max 0101 data

ACKNOWLEDGEMENT

The authors wish to acknowledge Lloyd Weida and Dave Garvin for measurements, Joe Trackim and Dave Potter for layout and the rest of the CDR design team: Larry DeVito, Declan Dalton, Todd Weigandt, Richard Soenneker and Stuart McCracken.

REFERENCES

[1] D. Dalton, K. Chai, E. Evans, M. Ferris, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, L. DeVito, “A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE J. of Solid-State Circuits., vol. 40, no. 12, pp. 2713-2725, December 2005.

[2] J. Kenney, D. Dalton, M. Eskiyerli, E. Evans, B. Hilton, D. Hitchcox, T. Kwok, D. Mulcahy, C. McQuilkin, V. Reddy, S. Selvanayagam, P. Shepherd, W. Titus and L. DeVito, “A 9.95 to 11.1 Gb/s XFP Transceiver in 0.13μm CMOS,” IEEE J. of Solid-State Circuits., vol. 41, no. 12, pp. 2901-2910, December 2006.

[3] L. DeVito, “A Versatile Clock Recovery Architecture and Monolithic Implementation,” in Monolithic Plase-Locked Loops and Cock Recovery Circuits, B. Razavi, Ed. Pistacaway, NJ: IEEE Press, 1996, pp. 405-420.

[4] R.B. Staszweski, C. Hung, D Leipold, P. Balsara, “A First Multigigahertz Digitally Controlled Oscillator for Wireless Applications,” IEEE Trans. Microwave Theory Tech., vol 51, no. 11, pp. 2154-64, Nov. 2003

[5] N. Da Dalt, C. Kropf, M. Burian, T. Hartig, H. Eul, “A 10b 10GHz Digitally Controlled LC Oscillator in 65nm CMOS,” ISSCC Dig. Tech. Papers, Feb, 2006, pp. 669-78.

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