Fig.1. Schematic sketch of ISEGaS MOSFET. Channel Length (L) = 100 nm, Dielectric Pocket Thickness (TS) = 20 nm, Shallow Extension Depth (TH) = 10nm, Junction Depth (Xj) = 30 nm, Tox1 = 2nm , Tox2 = 1nm,NA = 1x1017 cm-3.

Source

L

NA

ND+ ND

+TH

Gate

εox1 , tox1

εox2 , tox2

Xj

Wdx

y

Drain

Vbi Vbi+VDS

FBGS'GS VVV −=

At deplet ion edge,Wd

Potential = -Vsub

TS

12 oxox

sioxeff ttt

εε+=

2oxφ1oxφ

P-typeSubstrate

Abstract— The electrical behavior of deca-nanometer ISE

MOSFET with gate stack: ISEGaS has been investigated and a computationally efficient analytical model using Evanescent Mode Analyses (EMA), for solving two-dimensional Poisson’s equation in the channel region, has been presented for accurate prediction of surface potential, electric field, subthreshold current and threshold voltage. An important short channel effect (SCE) - Drain Induced Barrier Lowering (DIBL) has been included in the model in a physically consistent manner, using Voltage Doping Transformation (VDT) method. The obtained analytical results have been verified by ATLAS 2D: device simulation software.

Index Terms—ATLAS 2D, EMA, ISEGaS and VDT.

I. INTRODUCTION

s the Si MOSFETs are scaled ever close to their limits, a significant number of new technological

issues emerge. The field influence of the drain at the source side in scaled devices, however, poses a severe constraint on the device design. The drain-source lateral field affects the potential barrier height and consequently, punchthrough current arises as the drastic outcome of this lateral field effect. Among the many solutions offered by the research community to circumvent this problem, Insulated Shallow Extension (ISE) MOSFET with assimilated dielectric pocket as shown in Fig. 1, emerges as one of the promised candidate for planar devices.

In this work we present 2D analytical modeling in subthreshold region that can facilitate device design and technology selection. The electrical behavior of deca-nanometer ISE MOSFET with gate stack: ISEGaS has been investigated and a computationally efficient analytical model using Evanescent Mode (EMA) [1] has been presented. The model incorporates Drain Induced barrier Lowering (DIBL) effect using Voltage Doping Transformation (VDT) [2] method, which replaces the influence of the lateral S/D field by an equivalent reduction in the channel doping concentration. In the

The work of R. Chaujar was supported by the University Grants Commission.

R. Kaur, R. Chaujar, and R. S. Gupta are with the Semiconductor Devices Research Laboratory, University of Delhi, New Delhi 110021, India (e-mail: ravneetsawhney13@rediffmail.com;rishuchaujar@rediffmail.com; rsgu@bol.net.in).

M. Saxena is with the Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi 110015, India (e-mail: saxena_manoj77@yahoo.co.in).

subthreshold region of the ISEGaS MOSFET, the electrostatic potential is set by the boundary conditions of the linear Laplace equation ignoring the carrier and doping concentrations. Using the superposition principle, we can obtain 2D analytical solutions similar to [3]. The obtained analytical results have been verified by ATLAS 2D: device simulation software [4].

II. MANUFACTURING FEASIBILITY

The process flow for fabrication of ISE MOSFET structure is described in detail by Jurczak et.al [5] and [6]. In [5], following the well implantation and gate patterning, depression in the S/D region that determine the depth of dielectric pocket, were formed using anisotropic plasma etching. However, the described process requires fine tuning of process control parameters during dry etching to form the dielectric pocket. Thus, an advanced technique for fabricating ISE MOSFET is presented in [6]. The dielectric pocket is formed by forming an oxide layer over exposed source and drain regions in substrate. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode to form the dielectric pocket and a channel region between source and drain.

Subthreshold Performance Consideration of a Novel Architecture: ISEGaS deca-nanometer

MOSFET Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Senior Member, IEEE

A

978-1-4244-1728-5/07/$25.00 ©2007 IEEE

0

0.5

1

1.5

2

0 20 40 60 80 100Distance along the channel (nm)

Surfa

ce p

oten

tial (

V)

(b)

Line : AnalyticalSymbol : Simulatedεox1=3.9 (w ithout stack)

0

0.5

1

1.5

2

0 20 40 60 80 100Distance along the channel (nm)

Surfa

ce p

oten

tial (

V) Line : AnalyticalSymbol : Simulatedεox1=10 (w ith stack)

(a)

III. MODEL FORMULATION

The lateral influence of source and drain field onto the vertical growth of substrate depletion region is provided by the concept of VDT [2]. The lateral field influence initiated by the S/D junctions causes an equivalent reduction in effective substrate doping and the effective doping in the channel region is calculated as

DSsi

AA VqL

NN ∗−=′ ε2 (1)

* 2( ) 2 ( )( )DS DS bi c bi c bi DS cV V V V V Vηϕ ηϕ ηϕ= + − + − + − (2) Hereη is the spreading factor that accounts for transverse distribution of potential at the virtual cathode )(xvcφ [2].Then ))0(( vcsvc φφ = is taken proportional to cϕ , where

cϕ is the critical voltage needed for the onset of strong inversion. Usually FBc φϕ 2= , where FBφ is the Fermi potential andη is obtained by fitting process. The expression for depletion width using VDT is thus given by

si

sioxoGS

A

si

si

sioxd

tV

Nqt

Wε

ε−ϕ−

′ε

+ε

ε= )(

22

(3)

Using this depletion width dW , surface potential, electric field and hence, subthreshold drain current model is obtained. To obtain the two-dimensional potential distribution ),( yxψ in the channel, Poisson’s equation given by equation (4)

si

AqNdy

yxddx

yxdε

=φ+φ2

2

2

2 ),(),( (4)

is separated into 1D Poisson’s equation and 2D Laplace equation as

si

Al qNdy

ydε

=φ

2

2 )( (5)

0),(),(

2

2

2

2

=φ

+φ

dyyxd

dxyxd ss (6)

Thus

),()(),( yxyyx sl φ+φ=φ dWy

Lx≤≤≤≤

00

(7)

where, L is the channel length and Wd is the depletion depth obtained using VDT. Here

subsi

dAl V

WyNqy +

ε−′

=φ2

)()(

2

(8)

),(),(),( 21 yxyxyx sss φ+φ=φ (9)

( )∞

= π

−πχ+πχ

π ×=φ1 sinh

)(sinh2sinh1

1 sin),(r

LdWr

LydWr

rLyr

r

Lxr

s yx

(10)

( )∞

= π

−πχ+πχπ ×=φ

1 sinh

)(sinh2sinh3

2 sin),(r

dWLr

dWxLr

rdWxr

r

dWyr

s yx

(11) N’

A is the reduced doping; Vsub is the effective substrate-to-source voltage at the depletion edge and dW is the depletion depth obtained using VDT [2]. The obtained analytical results have been verified by ATLAS 2D: device simulation software [4].

IV. RESULTS AND DISCUSSION

Fig. 2(a) & (b) compares the simulated and modeled surface potential distribution of ISE MOSFET along the channel with and without gate stack. By using gate stack, we obtained physically thicker gate, while permitting the scaling of the Equivalent Oxide Thickness (EOT), which increases gate control over the channel. With increase in dielectric constant of upper gate oxide, the magnitude of minimum surface potential decreases and this leads to better gate controllability in the channel.

Further, Fig. 3(a) & (b) gives a good agreement of modeled and simulated electric field distribution along

Fig. 2 Surface Potential distribution along the channel for ISEGaS MOSFET for drain bias (VDS)=1.0V and gate bias( VGS)=0.1V. (a) With stack , EOT=1.78nm (b) Without stack . L=60nm & L=100nm,

ox1=3.9, Ts=20nm, TH=10nm and q M1=4.77 eV.

1.00E-11

1.00E-08

1.00E-05

1.00E-020.2 0.4 0.6 0.8 1

VGS (V)

I DS

(A/

m)

Line : AnalyticalSymbol : Simulatedεox1=10 (w ith stack)

VDS=1.0VVDS=0.1V

(a)

1.00E-11

1.00E-08

1.00E-05

1.00E-020.2 0.4 0.6 0.8 1

VGS (V)

I DS (A

/m

)

Line : AnalyticalSymbol : Simulatedεox1=3.9 (w ithout stack)

VDS=1.0VVDS=0.1V

(b)

Table 1 Subthreshold device behavior of ISEGaS MOSFET with variation in Ts and TH. L=100nm, ox2=3.9 and q M1=4.77 eV.

-2.5-2

-1.5-1

-0.50

0.51

1.52

0 20 40 60 80 100Distance along the channel (nm)

Surfa

ce E

lect

ric F

ield

(MV/

cm)

(a)

Line : AnalyticalSymbol : Simulatedεox1=10 (w ith stack)

-2.5-2

-1.5-1

-0.50

0.51

1.52

0 20 40 60 80 100Distance along the channel (nm)

Surfa

ce E

lect

ric F

ield

(MV/

cm)

(b)

Line : AnalyticalSymbol : Simulatedεox1=3.9 (w ithout stack)

the channel, thereby proving the effectiveness of the model.

Fig. 4(a) & (b) presents the comparison between the modeled and simulated subthreshold drain current (IDS)variation with VGS for 100nm-ISEGaS structure. The IDS -VGS curve, is further, used to evaluate the threshold

voltage using the constant current method and DIBL is, thus, measured as the difference between the linear threshold voltage at VDS=0.1V and saturation threshold voltage at VDS=1.0 V.

DIBL and subthreshold swing are the two important parameters to determine the short channel immunity of a device. The subthreshold performances of ISE devices for different Tside and Xe variations with and without gate stack are summarized in Table1.

It has been observed that with reduction in TH for same Ts, both DIBL and subthreshold slope decreases. This advantage results from the fact that with reduction in TH, the dielectric pillar penetrates more into the channel, thereby reducing the effective junction depth exposed to the drain bias

variations and hence, accounts for improved SCEs. However, with the penetration of these dielectric pillars into the channel, current flow is somewhat constricted resulting in higher threshold voltages.

Likewise, with the reduction in Ts for same TH,threshold voltage reduces with increase in DIBL and

subthreshold swing. Thus, lateral field penetration from S/D region can be reduced significantly due to the insertion of thicker side pillars and shallower extension depth. This lateral penetration is further reduced with the use of gate stack, as evident from the data in the Table 1.

V. CONCLUSION

An analytical model is developed for ISEGaS MOS technology using EMA for solving 2-D Poisson’s equation in the channel region. ISE devices is able to

offers high performance in terms of subthreshold slope,

DIBL and current drivability; enhancing the device immunity against SCEs, in nanometer regime. The results

εox2=3.9 VTH (V) S (mV/decade)

@VDS=0.1V @VDS=1.0V DIBL (mV/V)

@VDS=0.1V @VDS=1.0V Xe

(nm) Tside(nm)

Simulated Analytical Simulated Analytical Simulated Analytical Simulated Analytical Simulated Analytical

10 20 0.468 0.464 0.401 0.400 74.44 71.11 77.129 76.080 82.627 83.386 5 20 0.472 0.476 0.414 0.417 64.44 65.56 75.623 75.254 79.471 78.078

10 10 0.460 0.465 0.383 0.384 85.56 90.00 78.478 79.259 86.440 86.692 εox2=10(with stack)

10 20 0.440 0.439 0.394 0.394 51.11 48.89 75.646 73.995 71.613 72.902 5 20 0.443 0.433 0.404 0.376 43.33 43.33 70.503 71.658 73.259 75.055

10 10 0.434 0.431 0.381 0.384 58.89 52.22 72.623 70.196 74.490 75.339

Fig. 3 Electric Field distribution along the channel for ISEGaS MOSFET for drain bias (VDS) =1.0V and gate bias (VGS) =0.1V. (a) With stack, EOT=1.78nm (b) Without stack. L=60nm & L=100nm,

ox1=3.9, Ts=20nm, TH=10nm and q M1=4.77 eV.

Fig.4 Drain current (IDS) variation with Gate-to-Source voltage (VGS) for ISEGaS MOSFET. L=100nm, Ts=20nm, TH=10nm

ox2=3.9 and q M1=4.77 eV.

of analytical model agree well with the simulation data.

ACKNOWLEDGMENT

The authors would like to thank the Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India.

REFERENCES

[1] Te-K Chiang, “ Concise Analytical Threshold Voltage Model for Cylindrical Fully Depleted Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors,” Japanese Journal of Applied Physics, Vol. 44, pp. 2948-2952, 2005.

[2] T. Skotnicki., G. Merckel, and T. Pedron, “The Voltage-Doping Transformation: A New Approach to the Modeling of MOSFET Short-Channel Effects,” IEEE Trans. Electron Devices, Vol. 9, No. 3, pp 109–112, March 1988.

[3] G Katti , N. DasGupta and A. DasGupta, “Threshold Voltage Model for Mesa-Isolated Small Geometry Fully Depleted SOI MOSFETs Based on Analytical Solution of 3-D Poisson’s Equation,” IEEE Trans. Electron Devices, Vol. 51, No. 7, pp. 1169-1177, July 2004.

[4] ATLAS: 2D Device Simulator, SILVACO International 2002 [5] M. Jurczak, T. Skotnicki, R. Gwoziecki, M. Paoli, B. Tormen, P.

Ribot, D. Dutartre, S. Monfray and J. Galvier, “Dielectric Pockets – A New Concept of the Junctions for Deca- Nanometric CMOS Devices,”IEEE Trans. Electron Devices, Vol. 48, No. 8, pp. 1770-74, August 2001.

[6] H. Wang and Z. Wang , “DIELECTRIC PLUG IN MOSFETS TO SUPPRESS SHORT-CHANNEL EFFECTS,” United State Patent US 7,154,146 B2, Dec 26, 2006.