6.3

A 0.08p2-sized 8F2 Stack DRAM cell for multi-Gigabit DRAM Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, Min Huh, Gucheol Jeong,

Jaebuhm Suh, Hoyeop Kweon, Jaesung Roh, Kisoo Shin, and Sangdon Lee Device BT Team, Memory R&D Division, Hynix Semiconductor Co. LTD, San 136-1, Ami-Ri,

Bubal-Eun Ichon-Si. Kvungki-Do. 467-70 1 Korea

Abstract The first 8F2 Stack DRAM cell with 0.08pm’ size has

been successfully integrated employing poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. Cell transistor with W gate technology exhibits a sufficient saturation current(bP) of -40~1A with threshold voltage (Vbat) of 0.9V and satisfactory ring oscillator delay characteristics of - 5Ops.

INTRODUCTION The first principle in DRAM integration would be

miniaturization of cell in the viewpoint of cost reduction. In this study, we have integrated 0.08pm2-sized 8F2 stack DRAM cell. It is believed that this cell is smallest 8F2 cell that has been integrated ever. We have employed ArF patteming to get 100nm-cell resolution. Automatic OPC and manual OPC is applied to get expected CD for corelperi Tr with 0.17,m MFS. Noble exposure techaique of cross-pole illumination with PSM technique was adopted to enhance the exposure margin. As capacitor technology, Ru MIM concave capacitor technology was adopted. Key technology features compared to pervious work are listed in table 1 [ 11 : STI isolation, WPoly gate, poly-Si or Epi-Si plug cell contacts, E D 1 BPSG gapfiller, ED2 HDP oxide gapfiller, line-type SAC Storage node contacts, Ru MIM capacitor, DLM metallization and ArF patterning technique[2,3]. Introduction of new technology in patterning and capacitor technology is ascribed to integration work below lOOnm regime. Resolution limit of KrF lithography is expected to be around IlOnm, which means that sub lOOnm node needs new lithography technique beyond KIF lithography. As for cell contacts, conventional poly-Si plug has been compared to newly introduced Epi-Si plug while Epi-Si plug has more margin in cell contact resistance uniformity. In Ru MIM capacitor, Ru is adopted for bottom electrode, Ta205 for dielectric and TiN for Top electrode material. Concave capacitor structure is believed to have more margin in extendibility.

PROCESS SCHEME ArF photo-resist which is not so “resistant” to normal

etching chemistry needs noble hard mask etching scheme or resist hardening technology such as E-Beam curing, which will be summarized elsewhere[4]. As for module technology [Table 11, aiter trench isolation is done through I-type isolation mask, W/ploy gate stack is formed. N H 3 annealed W gate and conventional stack W gate showed similar R, result[l]. After selective oxidation is done, nitride gate spacer is formed for self align contact (SAC) barrier. In the case of Epi-Si plug, because of its higher thermal budget, landing plug is formed first prior to SourceDrain formation for peripheral MOS Transistor. Because channel engineering needs higher thermal budget such as 1000 “C , transistor degradation during sourceldrain

56 0-7803-7312-X/02/$17.00 02002 IEEE

RTA anneal can be avoided with landing plug formation prior to Source/drain formation. We may need optimal tuning of implantation condition for LDD and channel engineering. In the case of conventional poly plug, source/drain engineering is done prior to landing plug formation. Plug isolation is completed through CMP process , which is the same for both landing plug cell contacts and storage node contacts. Design scheme of BL Wiring for local interconnection is kept. MIM Concave capacitor structure is mechanically robust while getting smaller equivalent equivalent To, is key technology keeping leakage low far below 0.lfNcell.

RESULTS AND DISCUSSION Cross-sectional view for obtained cell structure is shown

in Fig. 1. 9Onm - sized cell Tr. shows about 4 0 ~ d current with operation condition of Vpp = 2.9V and v b b =

-0.8Vpig. 2, Fig. 31. Electrical Gate oxide thickness is 55A. Typical peripheral transistor performance was summarized in table 2. It is necessary to confirm AC characteristics of W gate Transistor fkom the viewpoint of reliability issue. Ring oscillator delay result of - 5Ops without signal fade-out is shown in Fig. 4. for current standard MOS transistor circuit. Cell contact resistance that is the summation of plug resistance and interfacial resistance shows better uniformity in Epi-Si plug case compared to conventional poly plug case. It is believed that tDPL issue could be overcome more easily in the Epi-Si plug case.pig. 51 P+ contact resistance which is critical for extendibility of buried channel PMOS showed < 2kWct.Fig. 61 MIM concave structure could be otained as shown in Fig. 7 and it showed capacitor leakage result less than 0.2fA /cell and To, eq of 12A [Fig. 81

CONCLUSION For the first time, a 0.08/rm2 sized 8F2 stack DRAM cell adopting W gate, poly landing plug, and MIM capacitor is successfully integrated. Its working is confirmed under easy function check mode. A 9Onm sized cell Tr shows -40,rlA Iop result. Ring oscillator delay of - 5Ops is observed. The technology developed in this work has good alignment with conventional technology except ibr ArF patteming technology and MIM capacitor technology, which are believed to be indispensable for extending to sub-1OOnm node DRAM fabrication.

REFERENCE [ l]Hyunpil Noh et. al. Symp. On VLSI Tech Dig., pp 25 - 26 (2001) [2] IC. H. Yoon, et. al., Symp. On VLSZTech. Dig., pp129

[3] 13eom-Jun Jin, et. al. Symp. On VLSI Tech. Dig. pp127

[4] Kwangok Kim, et. al. To bepublished.

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2002 Symposium On VLSI Technology Digest of Technical Papers

Table 1. Key process summary

Isolation pa-/ gapfiller

Gate ILDO

Landingplug

ILDl

0.1 15pmz 0.08pmZ -=;J-J- I-shape/ I-shape

w/ Poly W/Poly

Poly I

HDP IHDP

BPSG BPSG

Epi-Si E i-si HDp BPSG/H

DP

Transistor

NMOS

PMOS

Bitline I W I W

Remarks

Lg = 0.17 MII

v,, = 0.20 v ht = 360 / pm Lg = 0.17 pm V,, = 0.30 V

bt = 130 / Bm

Capacitor 1 T ~ ~ o ~ I T ~ ~ o ~

Itm 6pMOS 6nM05 size size

Barc 10 10.17 4 10.17

concave Concave 2Al(W 2Al(W

# o f Perid h i e S t w [ns] Ddq15tqe

WI 101 10.3 51.0

Fig. 4. Ring oscillator delay shown. # of inverter circuit =lo1 Gate delay per stage = 51ps. (a) Ring oscillator delay signal. @) Summary of oscillator delay measurement condition (c) DC parameters for transistors of ring oscillator circuit.

o p . I

Fig. 5. Comparison of Cell contact resistance between conventional poly plug and Epi-Si plug. Nitride spacer length is 30nm and Active open area between wordline is 50nm nominally.

. . . . . . . . 0 m 4m ,ma rm 74m

BLlAcnm k i n /cl)

(4 MlOBL Chan Rc @.17/n

I 8 IO ( 2 $ 4 16 ,a

M r i n Re (Ohmlu)

(b) Fig. 6 (a) Distributions for contact resistance of BL/N+ and BL/P+. BLC size = 0.15,m (b) Distribution of MlC/BL contact resistance M1C size = 0.17m

capacitor along to Wordline direction (Left) and along to Bitline direction Wght ). Ru is adopted as Bottom electrode and TiN as Top electrode /Storage node contact plug material / Storage node barrier metal.

V*.p.IVl

Fig. 8 Ru MIM Capacitor characte-ristics. Leakage characteristics where To, eq = 12 A

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