Advanced VLSI Design Sequential Logic Design CMPE 640
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1 Advanced VLSI Design CMPE 640 Sequential Logic Design Smaller Static Flip-Flops Positive feedback is not the only means to implement a memory function. A capacitor can act as a memory element as well. In this case, a periodic refresh is required (in the millisecond range) due to leakage (hence the word dynamic). Consider the following "cheaper" (1/2 transmission gate) positive level-sensitive static latch as a step toward deriving a dynamic FF: φ 1 φ 1 Out Static as long as φ 1 is kept low. When φ 1 is high, In is Out In sampled and stored on internal capacitors. A B Logic 1 degraded by V t .
Transcript of Advanced VLSI Design Sequential Logic Design CMPE 640
1
Adv CMPE 640
Sm
unction.
e) due to leakage (hence
evel-sensitive static latch
ng as φ1.
s high, In isnd stored onpacitors.
LV
anced VLSI Design Sequential Logic Design
aller Static Flip-Flops
Positive feedback is not the only means to implement a memory fA capacitor can act as a memory element as well.
In this case, a periodic refresh is required (in the millisecond rangthe word dynamic).
Consider the following "cheaper" (1/2 transmission gate) positive l
as a step toward deriving a dynamic FF:
φ1
φ1
OutStatic as lois kept low
When φ1 i
OutIn
sampled ainternal ca
A B
ogic 1 degraded byt.
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Adv CMPE 640
Sm
d reversing the clocks.
may cause two types of
hen φ1 and φ1 are both
d φ1 are high simulta-
Q
anced VLSI Design Sequential Logic Design
aller Static Flip-Flops
A master-slave FF is created by cascading two of these latches an
The problem with this latch is that φ1 and φ1 might overlap, which
failures:
Node A can become undefined as it is driven by both D and B w
high.
D can propagate through both the master and slave if both φ1 an
neously for a long enough period (race condition).
φ1
φ1QM
D
φ1
φ1A
N1
N2
A B
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Adv CMPE 640
Sin
signs.
anced VLSI Design Sequential Logic Design
gle Phase Clock Skew/Slew
Clock skew causes conflicts and transparency.
Clock slew (slow rise and fall times) can also cause transparency:
Clock skew is a dominant problem in current high performance de
φ1
φ1
Both n transistors are "on".
φ1
φ1
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Adv CMPE 640
Ps
skew.
is driven during tφ-1 and
Q
anced VLSI Design Sequential Logic Design
eudo-Static Two-Phase Flip-FlopsThe fix is to use two non-overlapping clocks φ1 and φ2:
A large tφ-12 allows proper operation even in the presence of clock
Note that node A floats (dynamic) during the time period tφ-12 but
tφ-2 (static).
Hence, the name pseudostatic.
φ2
φ1QM
D
φ1
φ2AA
φ1
φ2
tφ12tφ1
tφ2
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Adv CMPE 640
CMtapaths for microproces-
es are used).
(under worst-case condi-
Q
Vtp.
Q
els.
anced VLSI Design Sequential Logic Design
OS Dynamic Two-Phase Flip-FlopsThis version is simplier (6 trans) and is often used in pipelined dasors and signal processors.
Disadv: 2 non-overlapping clocks required (4 if transmission gat
These implementations MUST be simulated at all process cornerstions).
φ1
D
φ2
Degraded ’1’ values may increase static current if below
φ1
D
φ2
VDDVDDp leakers
p leakers provide fully restored logic lev
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Adv CMPE 640
Tw
tors N arent!
anced VLSI Design Sequential Logic Design
o-Phase ClockingClock skew/slew:
φ1 logic
large delay
φ1
φ2 logic
small delay
φ2
Both n-transisonoverlapping clocks: become transp
Overlap!
Slew
Skew
φ1
φ2
Excessive loadscan increaserise/fall times.
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Adv CMPE 640
C2
φ1VDD
φ1
GND
Q
φ1
φ1
anced VLSI Design Sequential Logic Design
MOS Register
C2MOS: A clever method which is insensitive to clock skew:
VDD
Dφ1
φ1
VDD
QD
Note: Dual phase version is identicalexcept φ2 and φ2 are used to drivethe n/p-trans in the right inverter.
φ1
φ1
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Adv CMPE 640
C2
f the clk edges (clock
VDD VDD
Q
0-0 overlap
0
anced VLSI Design Sequential Logic Design
MOS Register
C2MOS is insensitive to overlap as long as the rise and fall times oslew) are sufficiently small:
VDD
Dφ1
φ1
VDD
Q
φ1
φ1
VDD
D
VDD
Q D
1-1 overlap
1 1
No race is possible!
In order for Dto race to theQ, a pull-upfollowed by apull-down mustbe enabled.
0
Acts as a negative edge-triggeredmaster-slave D FF.
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Adv CMPE 640
C2
ull-up or the pull-down
ts a time slot in which
about 5 times the propa-
cially attractive in high
anced VLSI Design Sequential Logic Design
MOS Register
Races are just not possible since the overlaps activate either the pnetworks but never both simultaneously.
The inverters force 0-1 and 1-0 propagation modes only.
However, if the rise and fall times of the clock are slow, there exisboth n- and p-transistors are conducting simultaneously.
Correct operation requires the clock rise/fall times be smaller thangation delay through the FF.
This is not hard to meet in practical designs, making C2MOS espespeed designs where avoiding clock overlap is hard.
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Adv CMPE 640
Pip
a
blog
Reg
out
In
C3
Out
anced VLSI Design Sequential Logic Design
elining
The minimum allowed clock for the pipelined system is:
Implementation using pass-transistor based D latches
As indicated, races can occur when φ and φ overlap.
Reg
Reg
abs log
Reg
out+
Reg
Reg
a
babs+
Tmin tq max td,add td,abs td,log, ,( ) ts+ +=
φ φ
C1 C2F G
φ
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Adv CMPE 640
Pip
ons, F, implemented
rged as shown above.
elined datapaths by com-
OutC3
anced VLSI Design Sequential Logic Design
elining
C2MOS latches can be used instead, but ONLY if the logic functibetween the latches are non-inverting.
If F is inverting, and φ and φ overlap (1-1), then C2 is discha
NORA-CMOS (NO-RAce) targets the implementation of fast pip
bining C2MOS with np-CMOS dynamic function blocks.
φ
Inφ
C1 C2F Gφφ
φ
φ1
0 1
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Adv CMPE 640
Pip
t
φ-module
Out
φ-module
Evaluatingwhen φis 1.
anced VLSI Design Sequential Logic Design
elining with NORA-CMOS
PDNIn1In2In3
φ
φ
PUN
φ
φ
Ouφ
φ
Combo Latch
PDNIn1In2In3
φ
φ
φ
φ
In4
In4
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Adv CMPE 640
Pipdules.
hold mode, the other
n. When dynamic gates gate and between the last
plementationroblematic
anced VLSI Design Sequential Logic Design
elining with NORA-CMOSThe NORA datapath consists of a chain of alternating φ and φ mo
While one class of modules is precharging with its output latch inclass is evaluating.
Note that dynamic and static logic can be mixed freely.
Rule: # of static inversions between C2MOS latches should be eveare present, the # of static inverters between a latch and dynamic dynamic gate and latch should be even.
PDN
In1
In2
φ
φ
Outφ
φ
0-0 clock overlap This imis p
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Adv CMPE 640
Tr sufficient.
nsparent evaluate mode
ll-up network is still
constraints.
S latch
Out
anced VLSI Design Sequential Logic Design
ue Single-Phase Clocked Logic (TSPCL)The NORA design style can be simplified so that a single clock is
For the doubled n-C2MOS latch, when φ = 1, the latch is in the traand corresponds to 2 cascaded inverters (non-inverting).
When φ = 0, both inverters are disabled (hold mode) -- only the puactive.
The dual stage approach completely eliminates races.
This style combines the advantages of C2MOS and eliminates all
Outφ
Doubled n-C2MOS latch
φ φ
Doubled p-C2MO
φIn In
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Adv CMPE 640
Trtch.
e clock.
Out
Out
anced VLSI Design Sequential Logic Design
ue Single-Phase Clocked Logic (TSPCL)The one disadvantage is that 6 transistors (vs. 4) are needed per la
A further simplification is to control only the first inverter with th
φ φIn
PUN
PDN
Includelogic inthe latch
Staticlogic φ φ
OutφIn
φ-latch φ-latch
φIn
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Adv CMPE 640
Tred in half.
r and a loss in perfor-
ic (TSPC).its with a single clock.
anced VLSI Design Sequential Logic Design
ue Single-Phase Clock Logic (TSPC)This reduces the number of transistors and the clock load is reduc
Problem: not all node voltages experience the full logic swing.
Node A (for Vin = 0V) maximally reaches VDD - VTn.
This results in a reduced drive for the output NMOS transistomance.
This design methodology is called True Single-Phase Clock LogIt allows for the implementation of dynamic sequential circu
OutφIn
φ-latch
A
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Adv CMPE 640
Tr
ell.
-triggered
φQ
it-output latch
anced VLSI Design Sequential Logic Design
ue Single-Phase Clock Logic (TSPC)Edge-triggered FFs:
Split-output version reduces clock load in half, while performing w
φ
φ
D
Positive edge-triggered
φ
Qφ φ
φ
D
Negative edge
φ
φ φD
Positive edge-triggered
Q
Doublelatch versions
Spl
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Adv CMPE 640
Mo
e the circuit is triggered
state.by the circuit parameters.
in static memories for
anced VLSI Design Sequential Logic Design
nostable Sequential Circuits
A circuit that generates a pulse of a predetermined width every timby a pulse or transition event (one-shot).
The circuit has only one stable state -- the quiescent state.
The trigger causes the circuit to go temporarily into a quasi-stable
It returns to its quiescent state after a time period determined
Useful for address transition detection (ATD) to generate timing subsequent operations.
We've seen this version in edge-triggered FFs.
DELAYtd Out
In
td
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Adv CMPE 640
Mok to generate a pulse of
resistor R.
again (note In has
.
anced VLSI Design Sequential Logic Design
nostable Sequential CircuitsA second class uses feedback combined with an RC timing networ
fixed width.
Initially, In and Out are low and therefore A is high. B is high via
Pulsing In high causes A to go low, pulling node B with it.Node B gets pulled high again with time constant RC.Out goes low when B reaches VM, which causes A to go high
already gone low again).
The width (t2 - t1) is determined by the time-constant RC and VM
Unfortunately, VM is relatively sensitive to process variations.
C
A OutInB
In
B
t1 t2
Out
R
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Adv CMPE 640
As
e states with a period
n.
cillator
the chain.
anced VLSI Design Sequential Logic Design
table Sequential Circuits
A circuit with no stable states.The output oscillates back and forth between two quasi-stabl
determined by circuit parameters.
The main application of such a circuit is on-chip clock generatioWe already looked at the ring oscillator as an example.
The period T of the oscillation is:
where tp is the propagation delay of the composing gates.
v0 v1 v2 v3 v4
Ring os
T 2 tp N××= where N is the # of inverters in
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Adv CMPE 640
Aslock signals with differ-
quency is proportional to
Out
3
1 Iref
2
4
Polaritycorrectinginverter
Sharpensrise andfall times
anced VLSI Design Sequential Logic Design
table Sequential CircuitsBy tapping the ring oscillator at different stages, a wide range of cent duty-cycles and phases can be derived.
It is often desirable to tune the frequency of oscillation.
An example is a Voltage-controlled Oscillator (VCO), whose frethe value of a control voltage.
0 1 2 N-1
Iref
M5M
M
M
MM6
In
Vctrl
Currentstarvedinverters
Current sources
Controls value of Iref
Lowering the value of Vctrlreduces the discharge currentand hence tpHL.
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Adv CMPE 640
As
r M6 - M4.
rolled by Iref.
= IDS6 = Iref.
xists between Vctrl and
e range.
es of the current-stared
the chain.
anced VLSI Design Sequential Logic Design
table Sequential CircuitsCharging current is controlled via M5.
Iref is translated into a charging current through the current mirro
Here, M6 acts as a diode and sets a bias voltage VGS6, that is cont
With VGS4 = VGS6 and both devices operating in saturation, IDS4
Since both M3 and M5 operate in saturation, a quadratic relation e
Iref (and tp).
This allows the frequency of the VCO to be controlled over a larg
A Schmitt trigger is used to sharpen the weakened rise and fall timinverter.
Note that transistors M5 and M6 can be shared over all inverters in
