CROSSTALK AWARE BANDWIDTH MODELLING FOR VLSI RC GLOBAL INTERCONNECTS USING 2-Π MODEL

Presented By

Santosh Kumar Chhotray

National Institute of Technology, Durgapur

CONTENTS

Introduction Crosstalk noise Crosstalk noise effects Crosstalk noise model Proposed estimation method Result References Conclusion

INTRODUCTION

DSM Technology

CROSSTALK NOISE

-Unwanted coupling voltages-No. of metal layers-Density of integration-Reduction of spacing between

lines

CROSSTALK NOISE EFFECTS

-Noise on non-switching wires

-Increased delay on switching wires

-Limited bandwidth

CROSSTALK NOISE MODEL

Two partially coupled interconnects

PROPOSED ESTIMATION METHOD

Aggressor Waveform

0( )

dd aaagg

dd a

tV t

V t

V t

2

1( )agg dd

a

V s Vs

In S-domain

In Elmore delay model, the delay time between node na1 and node na2, D1→2 is represented as

1 2 1 1 2 3 2 2 3a a a c a a a c aD R C C C C R C C C

CONT.. Aggressor Waveform

Where

Now becomes

1 1 2 3 2 2 3a a a a c a a a c aR C C C C R C C C

Effective capacitance

1 1 2 3 2 2 3a a a c a a a c aT R C C C C R C C C

3 3dj a aT R C

1 1 2 3 2 2 3a a a a c a eff a a c a effR C C C C R C C C

a

3 3 1dj

TT

a eff aC C e

PROPOSED ESTIMATION METHOD

Analytic Waveform of Victim Interconnect

1 2 1 1 23 2

( ) ( )1

v v v v v cnoise agg

R R C s R R C sV s V s

as bs ds

1 2 3 1 1 3v v v v v c va R R R C C C C

1 1 2 2 3 3 3 3 3 2 1 2v v v v C v v v v v v c v vb R C R C C C R C R C C C R R

1 1 2 3 2 2 3 3 3v v v c v v v c v v vd R C C C C R C C C R C

CONT..

Now Vnoise(S) can be written as

where poles s1, s2 and s3 are roots are of . When relationship of s1< s2<< s3 is satisfied, the most dominant pole s3 is represented as 1/d. Replacing d by

Vnoise (S) obtained as

31 2

1 2 3

( ) ( )noise agg

KK KV s V s

s s s s s s

v

1 2( )

1v v c

noise ddv a

R R CV s V

s s

CONT..After solving with partial fraction

Now taking ILT

1 2 1( )

1v v v

noise c dda v

R RV s C V

s s

1 2( ) 1 v

t

tv vnoise c dd

a

R RV t C V e

DELAY ESTIMATION

Simplifying above equation

1 20.5 1 v

t

tv vdd c dd

a

R RV C V e

50%1 2

1(1/ )

2v a

cv v

t CR R

For delay estimation equating Vnoise(S)=0.5 Vdd

BANDWIDTH ESTIMATION

Rearranging above equation

Now replacing S by

1 2( )( )

( ) 1v vnoise

cagg v a

R RV sH s sC

V s s

1 2( )1

v vc

a v

R R sH s C

s

1 2

2 2( )

1c v v v

a v

C R R jH j

j

CONT..

Now to get 3db bandwidth

1 2

2 2

1

2 1

c v v

v v

C R R

3 2 22

1 22 2

adB

c v v a v

fC R R

RESULTSBandwidth for different value of R

CONT..

50% delay for different value of Rs

CONT..

CONCLUSION

For delay estimation

For bandwidth estimation

3 2 22

1 22 2

adB

c v v a v

fC R R

50%1 2

1(1/ )

2v a

cv v

t CR R

REFERENCES [1] Wu Shien-Yang, Liew Boon-Khim, Young K.L., Yu C.H., and Sun S.C.,

1999, “Analysis of Interconnect Delay for 0.18µm Technology and Beyond, IEEE International Conference on Interconnect Technology, pp. 68 – 70.

[2] Delmas-Bendhia S., Caignet F., Sicard E., 2000, “On Chip Crosstalk Characterization of Deep Submicron Buses”, IEEE International Caracas Conference on Devices, Circuits and Systems.

[3] Vittal A., Marek-Sadowska M., 1997, “Crosstalk Reduction for VLSI.” IEEE Trans. Computer Aided Design. Integrated Circuits System, Vol. 16. No. 3, pp. 290-298.

[4] Rubio A., Zu N. Itazaki. X., Kinoshita K., 1994, “An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits,” IEEE Trans. Computer Aided Design, Vol. 13, No. 3. pp. 387-394.

[5] Devgan A., 1997, “Efficient Coupled Noise Estimation for On-Chip Interconnects,” Proc. ICCAD, pp.147-151,.

[6] Sheehan B. N., 2000, “Predicting Coupled Noise in RC Circuits By Matching 1, 2, and 3 Moments,” Proc. DAC. pp. 532-535.

[7] Kar R., Maheshwari V., Mal A. K., Bhattacharjee A. K., 2010, “Delay Analysis for On-Chip VLSI Interconnect using Gamma Distribution Function”, International Journal of Computer Application, vol. 1, no. 3, Article 11, pp. 65-68.

CONT.. [8] Kar R., Maheshwari V., Maqbool Mohd., Mal A. K., Bhattacharjee

A. K., 2010 , “A Closed form Delay Evaluation Approach using Burr’s Distribution Function for High Speed On-Chip RC Interconnects”, IEEE 2nd International Advance Computing Conference (IACC 2010), Patiala, India, pp. 129-133, Feb. 19-20.

[9] Kar R., Maheshwari V., Reddy M. Sunil K, Agarwal V., Mal A. K., Bhattacharjee A. K., 2010 , “An Accurate Delay Metric for Global On-Chip VLSI RC Interconnects using First Three Circuit Moments”, 14th VLSI Design And Test Symposium (VDAT 2010), July 7-9, , India.

[10] Kawaguchi H., Sakuraai T., 1998, “Delay and noise formulas for capacitive coupled distributed RC lines,” in Proc. Asia-Pacific Design Automation conf., pp. 35-43.

[11] Sakurai T., 1993, “ Closed form expression for interconnection Delay, coupling, and crosstalk in VLSI’s,” IEEE Trans. on Electron devices, vol. 40, no1, pp. 118-124.

[12] Cong J., Pan D. Z., and Srinivas P. V., 2001, “Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization,” Proc. ASP -DAC, pp.373-378.

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