High aspect ratio 0.1 μm tungsten gates for InGaAs/InAlAs heterojunction transistorsD. M. Tennant, S. C. Shunk, M. D. Feuer, JM. Kuo, R. E. Behringer, T. Y. Chang, and R. W. Epworth Citation: Journal of Vacuum Science & Technology B 7, 1836 (1989); doi: 10.1116/1.584676 View online: http://dx.doi.org/10.1116/1.584676 View Table of Contents: http://scitation.aip.org/content/avs/journal/jvstb/7/6?ver=pdfcov Published by the AVS: Science & Technology of Materials, Interfaces, and Processing Articles you may be interested in Temperature dependence of ballistic mobility in a metamorphic InGaAs/InAlAs high electron mobility transistor J. Appl. Phys. 116, 044514 (2014); 10.1063/1.4891730 Irradiation effects in InGaAs/InAlAs high electron mobility transistors Appl. Phys. Lett. 79, 2279 (2001); 10.1063/1.1408904 0.1 μm AlGaAs/InGaAs high electron mobility transistor fabrication by the new method of thinned resist patternreversed by metal J. Vac. Sci. Technol. B 14, 3248 (1996); 10.1116/1.588815 Ultrafast 1.55μm photoresponses in lowtemperaturegrown InGaAs/InAlAs quantum wells Appl. Phys. Lett. 65, 1790 (1994); 10.1063/1.112870 Electron beam fabrication of highperformance InGaAs/InAlAs heterojunction insulated gate field effect transistorswith submicron refractory airbridge gates J. Vac. Sci. Technol. B 6, 1820 (1988); 10.1116/1.584160

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High aspect ratio 0.1 ..... m tungsten gates for InGaAs/lnAIAs heterojunction transistors

D. M. Tennant, S. C. Shunk, M. D. Feuer, J-M. Kuo, R. E. Behringer, T. Y. Chang, and R. W. Epworth AT&T Bell Laboratories, Holmdel, New Jersey 07733

(Received 2 June 1989; accepted 11 July 1989)

High aspect ratio submicron W gate structures as short as 0.1 pm have been made bye-beam lithography and reactive ion etching. An SF6/CHF3 gas mixture has been studied to limit the undercutting observed in SF 6 alone. Etch profiles in l-,um-high tungsten have been systematically studied as a function of gas composition and an optimum ratio found. Data will also be presented on etch selectivity, bias voltage effects, and overetching. High-performance InAlAs/InGaAs heterojunction-insulated-gate FETs (HIGFETs) incorporating W air-bridge gates as short as 0.3 ,urn have been made using this technology. These devices exhibit a unity current gain frequency j, of 80 GHz, as measured, and an estimated 118 GHz when corrected for pad capacitance. Both pinchoff characteristics and threshold voltage data have been measured for devices with gate lengths from 0.4 to 1.2 pm and are found to be suitable for enhancement mode operation.

I. INTRODUCTION

InGaAs channel FETs continue to be favored for high-speed performance due to their high mobility and high electron peak velocity. These properties improve with higher In con­tent, and therefore Ino.53 Ga0 .47 As grown latticed matched to InP and pseudomorphically grown on InP (with In frac­tions as high as 0.62) have recently been used to push the operational frequencies of discrete FETs. 1

-3 The use of InP

as a substrate material also invites future development of optoelectronic integrated circuits. InGaAs/InAIAs hetero­junctions are used since they exhibit a large conduction­band discontinuity for good carrier confinement and InAIAs exhibits a large Schottky barrier height.

InGaAs channel modulation-doped FETs (MODFETs) of both the lattice matched and pseudomorphic varieties have exhibited high de transconductances gm and unity cur­rent gain cutoff frequencies.ft, .,2,4 some in excess of 200 GHz. I Application of these transistors to direct-coupled FET logic (DCFL) circuits can, however, be problematic due to the sensitivity of threshold voltage on variations in the doping concentration and thickness in the InA lAs wide­band-gap layer after recess etching. Heterostructure-insulat­ed-gate FETs (HIGFETs) which use an undoped AlInAs wide-band-gap layer as an "insulator" on an undoped InGaAs channel have recently been demonstrated in the InGaAs/lnAlAs system as an alternate device with superior threshold uniformity and larger forward bias capability while also exhibiting high-speed performance.5 In addition, these devices should provide a more favorable threshold vol­tage for enhancement mode operation.

In this work we report on progress toward an optimized submicron HIGFET structure which has resulted from im­proved gate processing, use of a thin MBE-grown channel layer, and implementation of a graded-layer superlattice buffer layer. To improve the process used to form the refrac­tory air-bridge gates employed in these structures, a system­atic study of etch gas composition was made to improve ani­sotropy of the gate during pattern transfer.

II. DEVICE FABRICATION

Although the HIGFET process sequence is discussed in detail elsewhere,3 the principal processing steps are dis­cussed here to provide a context for the improvements which have been made. The epitaxial layers for the HIGFET struc­ture were grown by MBE on Fe-doped InP substrates and are shown schematically in Fig. 1. The upper layer consists of an unintentionally doped channel consists of an uninten­tionally doped Ino.52 Alo.48 As barrier layer 500 A thick. The channel copsists of an unintentionally doped Ino.53 Ga0.47 As layer 300 A thick. Various buffer layers have been used, but the most successful comprises a lattice matched Ino.52 Alo.48 As layer 600 A thick on a graded superlattice of alternating Ino.52 Alo.48 As and InGaAIAs (lattice matched, with Eg = 1 eV) to a total thickness of 2450 A. The n-type background carrier density in these layers is estimated at 3-5Xl015 cm-3

•

The refractory gate metal, W, is vacuum deposited by electron-beam evaporation while an in situ argon-ion mill is directed at the wafer during deposition. Varying the depo­sition rate while maintaining a constant 2 mA/cm2 Ar fiux was found to alter stress from highly tensile at high rates to compressive at low rates. A W deposition rate of8-10 A./s is near optimum allowing a 1.0,um thick film to be deposited with a residual tensile stress of about 2 X 109 dyn/cm2. The resistivity of the films were found to be improved and more repeatable by gettering of water and impurities via a depo­sition ofTi prior to W evaporation. Typical W film resistivi­ties are 6X 1O~5 n cm.

Nominal gate lengths of 0.1-1.0 ,urn are patterned using a JBX-SDII electron-beam lithography system at 50 kV to ex­pose a bilayer electron resist. 6 A Ni film typically 600 A thick is e-beam deposited and lifted off in acetone. Nickel was chosen as the reactive ion etch mask material because it has high dry etch resistance compared to W, yet it is remov­able noninvasively.

Pattern transfer was achieved by reactive ion etching us­ing the SF6 :CHF3 gas mixtures described below.

1836 J. Vac. Sci. Technoi. B 7 (6), Nov/Dec 1989 0734-211X/89/061836-05$01.00 @ 1989 American Vacuum SOCiety 1836

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1837 Tennant et al.: High aspect ratio 0.1 Jlm tungsten gates

A refractory gate metal such as W is needed because it also serves as a self-aligned ion implantation mask in order to minimize the source and drain resistances. These resistances would otherwise be large since unlike a MODFET structure, the barrier layer is undoped. The Si .~. implant is performed at 50 kV with a ftucnce of 2 X 1013 /cm2

. The nickel etch mask is next removed in dilute HNO, without any measura­ble effect on the W gate.

An implant activation anneal is then performed in an in­coherent quartz lamp rapid thermal annealer (R T A) at 700°C for 10 s in forming gas using a proximity cap ofGaAs.

Next the InAIAs layer is reactive ion etched in CC12F2 :He:02 (1:1:0.63).7 Ohmic contacts patterned by photolithography are thermally deposited in a layered struc­ture comprising Au/Ge/ AulNiI Au in layer thicknesses of 140/140/140/110/2000 A, respectively. A low-temperature sinter of 420 cC for 25 s is performed in forming gas on a graphite strip R T A to improve contact adhesion. Typical contact resistances are La n for 100,um wide devices.

Barrier

Channel

Buffer

x4

xG Superlattice

Buffer

2450 A

xa

x10

1837

FIG. l. Schematic of MBE-grown HIGFET layer structure.

The final process step is the mesa isolation etch which forms air-bridge spans in the gates. The InGaAs is chemical­ly etched in 38: 1: 1 H 20:H,P04:HzO z to form the mesas.

III. TUNGSTEN ETCHING

Since the formation of high aspect ratio refractory gate structures is critical to making HIGFETs practical, we have studied various parameters affecting etch profiles of tung­sten. Earlier processing of W gate devices revealed signifi­cant undercutting of the mask material during reactive ion etching (RIE) in SF 6.

3 While the SF 6 readily etches through the full thickness of the deposited Wand exhibits good selec­tivity over the InAIAs, the undercutting prevents full height gates shorter than D.5/1m from forming. We have studied anisotropy changes which result from the addition of various fractions of CHF1 to SF 6 . All of the etch tests reported were performed in a parallel plate diode rf reactor. The cathode

FIG. 2. Electron micrographs of etched tungst~n gates (nominally O.2/1111 long) etched in SF" and varying percentages ofCHF,. (a) 0%, (b) 11 %, (c) 33%,

and (d) 50%.

J, Vac. Sci. Techno!. e, Vol. 7, No.6, Nov/Dec 1989

~ . ." .-.".".-... ' •.•.•.• -." •.• "." •.•.• -•.• -.-•.•.• ~.: •.• -.-.".-.".-.-••• -.-..... -••••.....••••• _ •.• n,. L_ .. , •• ~'--'-' ~H""~"' ••••••••• , .• ".,y .•. ~_ •. '_r.".~ •.. Redistribution subject to AVS license or copyright; see http://scitation.aip.org/termsconditions. Download to IP: 129.105.215.146 On: Sat, 20 Dec 2014 00:57:50

1838 Tennant et sl.: High aspect ratio 0.1 pm tungsten gates

.50r-----,-----.------,-----,~==~

/<;~:.:.~.:;.;;.2·· .40 .30

/ / /' ,/ ...... .

. 10 /' / ....

.20

O~. -------,.L-.~"';"'."". ------------J , ...,/ .. )

-.10 /' ..... / / .... /.

-.20 /. .... " .... ~ NOMINAL .10p,m -----

-.30 ",-;i.':'--.40 /

.15

.20

-.50 .25 -.60 '---_-'--___ ....L.... ___ -'-__ --L __ --..I

o 10 20 30 40 50

VOLUME PERCENT OF CHF3 IN SF6

FlG. 3. Deviation of the base from the mask after etching plotted as a func­tion of gas composition for four different gate lengths.

was covered with a silicon wafer and, unless stated other­wise, was maintained at a dc self-bias of 110 V. Total flow rates were maintained at about 10 sccm. End point detection was performed via changes in reflectance from a ReNe laser monitored by a power meter and plotted real time on a chart recorder. Also unless stated otherwise, all samples were overetched by 25% based on the time of the end point. For this etch study, Ni masks patterned on 1 pm thick W on GaAs were used.

Figure 2 is a series of electron micrographs which illus­trates qualitatively the overall effect of increasing the frac­tion ofCHF3 • For a nominal mask dimension ofO.2pm, the footprint at the base of the gate is observed to vary from 0.15 due to an undercut in the pure SF 6 to 0.25 pm due to an overcut in 50% CHF3 • We also observe that in alI cases a neck forms in the etched profile. The position of this neck changes curiously in that for pure SF 6 it is located repeatably near the midpoint in the profile, while the addition of even a small fraction of CHF3 causes the neck to appear immedi­ately beneath the Ni mask. In all cases, however, this neck limits the minimum gate length which can be practically formed. When the neck becomes vanishingly thin, the upper portion of the gate topples over resulting in a misshapen and eroded gate.

In all, gate lengths of 0.25,0.20,0.15, and 0.10 11m were patterned with Ni masks and etched in CHF3 :SF6 flow rate ratios ofO, 1 :8, 1 :3, and 1 :2. Figure 3 quantifies the deviation of the footprint width from the mask width. Interpolation of this data indicates zero deviation should occur at about 15%-20% CHF3 content. Since a slight negative deviation was desirable for the FET gates in this report, the 1:8 mix­ture was judged near optimum. Electron micrographs of all four gate lengths etched in the 1 :8' mixture are shown in Fig. 4. One unexpected result is the decrease in the relative nar­rowing in the neck region at the shorter gate lengths. This effect was clearly observed for gas mixtures up to 33% CHF3 •

While the etch rate of Wand the selectivity over Ni and InAIAs for these mixtures arc excellent, they do, in general, decrease as the CHF 3 fraction increases. In SF 6 alone, the

J. Vac. Sci. Technol. B, Vol. 7, No.6, Nov/Dec 1989

1838

FIG. 4. Electron micrographs of profiles of 0.25,0.20,0.15, and 0.10 J-lm (nominal) gates etched in 1:8 CHF,/SFo'

selectivity over Ni is 146: 1 and over InAIAs is 47: 1. When the CHF3 flow is increased to 50%, the selectivity over InAIAs decreases to 27:1. Even this decreased value is suffi­cient to easily allow etch stoppage in an InAlAs barrier layer only a few hundred angstroms thick. To determine process latitude, profiles were evaluated after an excessive overetch time for the 1:8 mixture. After a 95% overetch, there were no significant qualitative changes in the profiles. While there were only small changes in the overall width (about 5 % ), the substrate continues to etch (albeit slowly) and should be considered in the case of thin barrier layers.

It is important to note that the specific undercut and over­cut results quoted here are certain to be history dependent. The polymer formation which accompanies CHFl etching deposits in the chamber and can change the defacto compo­sition of the gas mixture. In general, the curves plotted in Fig. 3 would be expected to shift to the right for a "clean" system and to the left for a polymer-laden system. A corre­spondingly larger undercut is observed for example in an SF 6 dedicated system prior to CHF 3 introduction. The sys­tematic behavior of the profile dependence is quite reproduc­ible, however, when a standard chamber preparation (e.g., a standard oxygen plasma clean) precedes etching.

IV. DISCUSSION

Figure 5 is a series of electron micrographs of representa­tive air-bridge gate HIGFETs of various gate lengths fabri­cated by the procedure described above. The gate lengths in these completed devices measure 1.1,0.5,0.3, andO.12l1m at

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1839 Tennant et al.: High aspect ratio O.1jtm tungsten gates

FIG. 5. Scanning electron micrographs of (a) 1.2 pm. (b) 0.5 .am, (c) 0.3 /l.m, and (d) O.12pm gate length HIGFETs.

the top and are all full height. Devices with gate lengths of 0.3 pm and longer exhibit very good dc and high-frequency performance. Shorter devices consistently fail due to lateral ion implantation straggle during the formation of the self­aligned source and drain. The unity current gain cutoff fre-

HIGFET ft VS.

•

Gale Length

lj-_. --1 - Model

" Measured .. .. Corrected

2

FIG. 6. Summary of unity current gain cutotffrequency,j, as a function of physical gate length for e-beam patterned HIGFETs. The dashed line repre­sents a simplified velocity saturation model with zero parasitics.

J. Vac. Sci. Technol. S, Vol. 7, No.6, Nov/Dec 1989

~ w 0.0

~ o > Cl - 0.5 .J o I (J) w a: i!= -1.0

GATE LENGTH (I'm)

;> E

150 ;; o j::: « iI'

100 ;; Cl .J o r <I) w

50 a: I f-

1839

FIG. 7. Average threshold voltage (left scale) and standard deviation (right scale) plotted as a function of gate length.

quency j; is plotted as a function of gate length in Fig. 6. The highest measured value of 80 GHz was obtained for the 0.3 pm transistor, while 50 and 27 GHz were measured for the 0.5 and 1.1,lm devices, respectively. Since very large probe pads are used in experimental designs, pad capacitance can obscure the intrinsic high performance of the narrower de­vices. For this reason microwave results are often reported for pad corrected cutoff frequency data. To simplify com­parison with the literature, both the measured and pad cor­rected values are plotted in Fig. 6. The j, for the O.3-pm channel device increases to 118 GHz, while that for the 0.6 and 1.1 pm devices increase to 70 and 30 GHz, respectively. A simplified velocity saturation model with zero parasitics is plotted (dashed line) for comparison.

These data and dc measurements of J- V curves indicate substantial overall improvement in performance of these FETs over earlier results. The high aspect ratio gates better mask SID implants, resulting in less overlap of gate and drain and less threshold shift. The thin channel provides better gate control resulting in sharp pinch off. Figure 7 shows average threshold voltage as a function of gate length for five to ten devices at each gate length. For these devices, gate lengths greater than 0.6 pm exhibit threshold voltages suitable for application to high-speed DCFL. Threshold de­viation (0') is plotted for each gate length. Uniformity is shown to be excellent at about 30 m V, independent of gate length. In addition to the noted improvement in threshold, the wide-band-gap superlattice buffer has lowered the out­put conductance in these samples. The 0.7 pm gate length device, for example, had a measured gOut = 20 mS/mm at Vg = 0.5 V. While a more complete reporting of de charac­terization of these device is made elsewhere,5 these results show great promise for this class of heterojunction transis­tors.

v. CONCLUSIONS

The InGaAs/lnAlAs HIGFET fabrication process de­scribed successfully combines 1 ;.tm thick W air-bridge gates patterned by electron-beam lithography and RIE with self­aligned source/drain implants and RTA activation.

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1840 Tennant eta!.: High aspect ratio 0.1 pm tungsten gates

The use of a sufficiently thin channel layer has improved the pinchoff characteristics over preliminary device reports. In addition, threshold voltages suitable for use in enhance­ment mode transistors were demonstrated for gate lengths greater than 0.5 pm. Uniformity of threshold voltage was found to be excellent for the available sampling of devices at each gate length. The results of the process studies indicate that air-bridge gates down to 0.1 f-lm can be made in 1 pm thick tungsten and are very robust. The best etch results were obtained by adding 11 % CHF] to SF6 (by flow rate) during pattern transfer.

High-performance microwave results were obtained from these simple HIGFET structures. In particular an J, = 80 GHz was obtained for the Lg = 0.3 pm devices as measured and is estimated at 118 GHz when corrected for pad capaci­tance. These microwave results are comparable to the best MODFET results at these gate lengths.

The use of an improved buffer and thin channel signifi­cantly improved these values over earlier results. Further process advances will be required to take full advantage of 0.1 f-lm gate HIGFET process, however. For example, the lateral straggle of the SID implants under the gate needs to be minimized by using lower implant energies and using a side spacer similar to that used in silicon MOSFETs. This

J. Vac. Sci. Technol. e, Vol. 7, No.6, Nov/Dec 1989

1840

side spacer would prevent shorted channels, lower the gate capacitance, and reduce threshold shifts occurring in the shorter gate devices.

In addition to the further optimizing steps described above, the HIGFETs described in this work will also exhibit enhanced high-frequency performance when pseudomor­phic InGaAsl AIGaAs heterostructures become available. Future work will concentrate on these improvements as well as pursuing scaled p-channel HIGFETs, the second key step toward complementary logic.

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