ECE 471/571 Energy-E cient VLSI - Oregon State...
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ECE 471/571 Energy-Efficient VLSI Homework 1 Solutions 1. (a) NMOS: V DS >V GS - V T = ⇒ saturation. I D = 1 2 k 0 n W L (V GS - V T ) 2 (1 + λV DS ) = 283.3μA PMOS: |V DS | > |V GS - V T | = ⇒ saturation. I D = 1 2 k 0 p W L (|V GS |-|V T |) 2 (1 + λ|V DS |)=0.17μA (b) NMOS: V DS <V GS - V T = ⇒ linear. I D = k 0 n W L {(V GS - V T )V DS - V 2 DS 2 } = 447.8μA PMOS: |V DS | > |V GS - V T | = ⇒ linear. I D = k 0 p W L {(|V GS |-|V T |)|V DS |- V 2 DS 2 } = 64.8μA (c) NMOS: V DS <V GS - V T = ⇒ linear. I D = k 0 n W L {(V GS - V T )V DS - V 2 DS 2 } =1.38μA PMOS: |V DS | > |V GS - V T | = ⇒ linear. I D = k 0 p W L {(|V GS |-|V T |)|V DS |- V 2 DS 2 } = 36.75μA 2. (a) I D =0A, V D = -3.3V (b) Reverse biased (c) W j = s 2 Si q N A + N D N A N D (φ 0 - V D )=1.108μm Si = 11.7 × 0 = 11.7 × 8.854 × 10 -12 F/m =1.036 × 10 -10 F/m q =1.6 × 10 -19 C (d) C j = Si A D W j =1.122fF 1
Transcript of ECE 471/571 Energy-E cient VLSI - Oregon State...
ECE 471/571 Energy-Efficient VLSIHomework 1 Solutions
1. (a) NMOS: VDS > VGS − VT =⇒ saturation.
ID =1
2k′nW
L(VGS − VT )2(1 + λVDS) = 283.3µA
PMOS: |VDS| > |VGS − VT | =⇒ saturation.
ID =1
2k′pW
L(|VGS| − |VT |)2(1 + λ|VDS|) = 0.17µA
(b) NMOS: VDS < VGS − VT =⇒ linear.
ID = k′nW
L{(VGS − VT )VDS −
V 2DS
2} = 447.8µA
PMOS: |VDS| > |VGS − VT | =⇒ linear.
ID = k′pW
L{(|VGS| − |VT |)|VDS| −
V 2DS
2} = 64.8µA
(c) NMOS: VDS < VGS − VT =⇒ linear.
ID = k′nW
L{(VGS − VT )VDS −
V 2DS
2} = 1.38µA
PMOS: |VDS| > |VGS − VT | =⇒ linear.
ID = k′pW
L{(|VGS| − |VT |)|VDS| −
V 2DS
2} = 36.75µA
2. (a) ID = 0A, VD = −3.3V
(b) Reverse biased
(c)
Wj =
√(2εSiq
NA +ND
NAND
)(φ0 − VD) = 1.108µm
εSi = 11.7× ε0 = 11.7× 8.854× 10−12F/m = 1.036× 10−10F/m
q = 1.6× 10−19C
(d)
Cj =εSiAD
Wj= 1.122fF
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(e) Lower reverse-biased voltage leads to reduced width of depletion region,Wj. Effectively as plates of capacitor are brought closer together, capaci-tance Cj increases.
3. VDS > VDSAT =⇒ velocity saturation.Assuming for all 5 cases that Vmin = VDSAT = 0.6V ,
In cases 1-3,VBS = 0 =⇒ VT = VT0.
Using ID = k′W
L{(VGS − VT )Vmin −
V 2min
2}(1 + λVDS)
W
L= 15, VT0 = 0.44V, λ = 0.08V −1
In cases 4-5,Substituting previously found values and usingVT = VT0 + γ(
√| − 2ΦF + VSB| − (
√| − 2ΦF )
|2ΦF | = 0.6V, γ = 0.3V12
4. (a) VD = VDD − IDRD = 2VFor saturation, VDS > VGS − VT =⇒ VD > VG − VT∴ NMOS is in saturation region.
ID =1
2k′W
L(VGS − VT )2 = 50µA
VS = 1.3V
(b) VD = VDD − IDRD = 1VFor saturation, VDS > VGS − VT =⇒ VD > VG − VT∴ NMOS is in linear region.
ID = k′W
L{(VGS − VT )VDS −
V 2DS
2} = 50µA
VS = 0.93V
(c) Based on equation ID = 12k′nWL (VGS − VT )2(1 + λVDS), λ 6= 0 means ID has
to increase. However, since current source fixes ID to 50µA, VGS needs todecrease by increasing VS. So VS would increase.
5. (a) For short-channel, fixed-voltage scaling:
S =0.18µ
0.12µ= 1.5
2
A′ =A
S2= 0.311mm2
P ′ = P = 0.4mW/MHz × 100MHz = 40mW(P
A
)′= 128.62mW/mm2
(b) General scaling: U =1.8
1.5= 1.2
P ′ =P
U 2= 27.78mW(
P
A
)′= 89.32mW/mm2
(c) f ′ = f × S = 150MHzAssuming dynamic power dominates,P150 = P100 × S = 41.67mW(P150
A
)′= 133.99mW/mm2
(d) Since power density scales byS2
U 2:(
P150
A
)′=
(P100
A
)× S2
U 2S =
P100
A
U 2 = S3
U = 1.837
U =1.8
V ′
V ′ ≈ 1V
6. (a) Assuming long-channel, fixed-voltage scaling:S = 2.5f ′ = f × S2 = 625MHz
P ′ = P × S = 25W
(b) Full-scaling (since U = S = 2.5):f ′ = f × S = 250MHz
P ′ =P
S2= 1.6W
(c) To keep power constant:S
U 3= 1 =⇒ U = 1.36
V ′ =V
U= 1.84V
3
f ′ = f × S2
U≈ 460MHz
7. (a) Device is off while VG < VT .For VG = 0→ VT : CT = CT (1)VG = VT → 2VT : CT = CT (2)
t1 = CT (1)VTIin
t2 = CT (2)2VT − VT
Iin
∴ t = t1 + t2 = [CT (1) + CT (2)]VTIin
(b) Csb, Cdb do not contribute to gate capacitance.While device is off, VG < VT , Cgb contributes to CT .During VT < VG < 2VT , Cgb falls to zero.
0 < VG < VT =⇒ CT = CT (1) = CoxWL + W (CGD0 + CGS0) VT <
VG < 2VT =⇒ CT = CT (2) =2
3CoxWL+W (CGD0 + CGS0)
(c) Device is always off. Cgs, Cgb, Csb do not have connection to drain node.Overlap of Cgd and varying Cdb make up CT .
CT = WCGD0 +KeqCj0 +KeqswCjsw0
Cj0 = CjAD
Cjsw0 = CjswPDCT = WCGD0 +KeqCjAD +KeqswCjswPD
where,
Keq =−Pmj
B
2VT (1−mj)
[(PB − 2VT )(1−mj) − (PB)(1−mj)
]Keqsw =
−Pmjsw
B
2VT (1−mjsw)
[(PB − 2VT )(1−mjsw) − (PB)(1−mjsw)
]
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