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Design GaN PA MMICs Liam Devlin [email protected]
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Transcript of Design GaN PA MMICs - MWE Mediamwemedia.com/interlligentrf/LDevlin.pdf · GaN PA Design –unit...

  • Design GaN PA MMICs

    Liam Devlin

    [email protected]

  • Overview

    Brief introduction to the GaN transistor

    Basic GaN PA design approach single transistor example #1

    Thermal considerations

    Three GaN PA MMIC design examples:

    Example #2; 15GHz PA for LoS links

    Example #3; 2-18GHz NDPA for broadband operation

    Example #4; 25W X-band PA for radar applications

    Conclusions/summary

  • GaN Transistor Overview

    GaN is a wide bandgap material (bandgap of 3.4eV compared to

    1.4eV for GaAs)

    Source coupled field-plate reduce the fields at the surface at high

    drain-gate voltages, increases the breakdown voltage of the

    transistor.

    Source FP also increases the gate-source capacitance

  • GaN Transistor Overview

    G28V4 (0.25m) 4x75m Cree GaN HEMT

    Note high knee voltage (~ 5V)

  • GaN PA Design

    How GaN HEMT PAs differ to GaAs PHEMT PAs:

    Operating voltages are significantly higher (typically 20V to 40V

    compared to 4V to 12V)

    Power densities (output power per mm of gate width, are

    higher)

    Supply currents can be much higher

    Thermal conductivity of the SiC substrate is higher than GaAs

    Allowable channel temperature of the transistors is significantly

    higher

    Obviously there is some interaction between these and

    together they form the reasons why GaN MMICs can be

    used to realise higher power amplifiers than GaAs

  • GaN PA Design

    One of the first steps is selection of device and bias

    Larger transistors (higher total gate width) can produce

    higher output power levels, but:

    Available high frequency gain degrades as transistor size

    increases

    Adequate gain must available across the band of interest

    Adequate thermal performance must be ensured (affected by

    transistor size and bias, more on this later)

    For a 0.25m GaN on SiC process, 28V Vds and

    100mA/mm quiescent bias is reasonable starting point

  • GaN PA Design unit width

    Gmax versus frequency, 4-finger transistors biased at

    28V Vds and 100mA/mm Ids; various unit gate widths

  • GaN PA Design number of gate fingers

    Gmax versus frequency, transistors with 2, 4 6 and 8 finger biased

    at 28V Vds and 100mA/mm Ids, unit gate width fixed at 200m

  • GaN Power Amplifier Example #1

    Target: 4W at X-band (10 to 11.5GHz), using Crees G28v4 0.25m

    process

    Selected device size: 8x120m biased at +28V Vds, 100mA/mm Ids

  • GaN Power Amplifier Example #1

    Add input resistance for in-

    band stability:

    1.5 series resistor (RHS)

    Plus 16 shunt resistor (below)

  • GaN Power Amplifier Example #1

    Load-pull simulations at 4dB compression

    Shows +36.4dBm potential output power @ 49% efficiency

    Harmonic impedances can also be considered

  • GaN Power Amplifier Example #1

    X-band GaN PA simplified schematic:

  • GaN Power Amplifier Example #1

    X-band GaN PA small-signal simulations:

  • GaN Power Amplifier Example #1

    X-band GaN PA large-

    signal simulations:

  • GaN Thermal Consideration

    GaN transistors are able to operate reliably at much higher

    junction temperatures than GaAs (around 225C to 275C

    compared to 125C to 175C).

    However, they also operate at much higher power densities

    and good thermal design is essential

  • GaN Thermal Consideration

    The designer must to ensure that the transistors are operating

    at a sufficiently low junction temperature to provide adequate

    reliability.

    Channel temperature is affected by:

    substrate thickness

    device layout

    ambient/base-plate temperature and the total power dissipated in

    the device

  • GaN Thermal Consideration

    Thermal conductivity of SiC is very good but reduces with

    increasing temperature

    0

    0.05

    0.1

    0.15

    0.2

    0.25

    0.3

    0.35

    0.4

    0.45

    0.5

    0

    0.5

    1

    1.5

    2

    2.5

    3

    3.5

    4

    4.5

    5

    0 50 100 150 200 250 300

    GaA

    s Th

    erm

    al C

    on

    du

    ctiv

    ity

    (W/d

    egC

    .cm

    )

    SiC

    Th

    erm

    al C

    on

    du

    ctiv

    ity

    (W/d

    egC

    .cm

    )

    Temperature (degC)

    SiC

    GaAs

    This means that thermal impedance of GaN transistors and

    MMICs is temperature dependent

  • GaN Thermal Consideration

    Channel temperature rise versus power density for a packaged

    Cree GaN transistor

  • GaN PA Design Example #2

    Parameter Target Specification

    Frequency 14.5-15.35GHz

    Gain >20dB

    OIP3 45dBm at +22dBm per output tone

    Psat 38dBm

    PAE 35%

    Chip Area

  • GaN Process for Example #2

    Crees 0.25m GaN on Silicon Carbide

    4 x 250m transistor 4W/mm of RF output

    power

    Inter-source vias for low source inductance

    Wide gate spacing for improved thermal

    performance

    PDK able to account for thermal effects on RF

    performance

  • Transistor Selection, Example #2

    4 x 250m transistor (1mm total gate width)

    Initial bias: Vds: 28V, Ids: 100mA

    Device is unconditionally stable above 12.5GHz

    Gmax = 14dB at 15GHz

    Estimate of achievable stage gain is 11-12dB

    Implementation losses due to:

    Matching

    Bias circuitry

    Gain flattening

    LF stabilisation network

  • Preliminary Simulations: Output match

    Shunt inductor for conjugate match to 50

    Lshunt ~ 0.3nH

    Benefit of GaNs high voltage operation

    Much higher output impedance compared to

    comparable devices in competing

    technologies

    Allows simpler matching structures and

    broader band operation for a given power

    level

  • Preliminary Simulations: Load Pull

    Psat: 36.2dBm (4W) with Yout= 0.021-j0.041 50 // ~0.3nH

    PAE: 46.8% with Yout= 0.014-j0.036 70 // ~0.3nH

    OIP3: 43.1dBm with Yout= 0.007-j0.036 140 // ~0.3nH

  • IC Layout

    Note: Iq increased from initial design to 130mA/mm

  • Size comparison with similar GaAs device

    Area of a similar

    linearity

    amplifier in

    GaAs

    Area of the

    two-stage

    GaN amplifier

  • Simulated Performance, Example #2

    Pout at 3dB compression

    & corresponding PAE

    OIP3

  • Simulated Performance Summary

    Parameter Target Specification Simulated performance

    Frequency 14.5-15.35GHz 14.0-16.0GHz

    Gain >20dB 22.1dB +- 0.4dB

    Input Return Loss >15dB (14.5-16.2MHz)

    Output Return Loss >14dB (14.5-15.6MHz)

    OIP3 at +22dBm per output tone

    45dBm 46dBm

    Psat 38dBm >38dBm

    PAE 35% >36%

    Chip Area

  • Higher Order Modulation Simulations

    QAM-256 at 6dB back-off from P1dB at 130mA/mm

    EVM = 2.3%

  • Design Example #3

    A Non-Uniform Distributed Power Amplifier (NDPA).

    Design demonstrates that GaN allows high power to be

    achieved over a wide band-width. Uses Qorvos 0.25um GaN

    on SiC process and designed using Keysights ADS2013

    Typical Performance Outline:

    2 to 18GHz Bandwidth

    10dB Gain (small signal)

    7W (+38.5dBm) Output Power at 3dB compression

    25% Power Added Efficiency at 3dB compression

  • Design Example #3

    Features of chosen architecture:

    NDPA using 10 devices selected for wide band-width and high power.

    Characteristic impedance of drain line is tapered allowing each device to work

    into a near optimum load impedance.

    Optimum load is around 100 for a 1mm device biased in class AB from a 30V

    supply.

    Generally, drain line widths get narrower as we move away from the output

    toward the input.

    Device furthest from the output made larger than the others, hence Non-

    Uniform.

    This reduces required load impedance at that point such that highest impedance

    drain line still meets process design rules for minimum width.

    Series MIM capacitors on gates help to increase band-width at the expense of

    gain.

    Value of these capacitors can be varied along the line to ensure a similar drive

    level at each device.

  • Detailed Design

    Circuit schematic:

    RF In

    RF Out

    Vd

    Vg

  • MMIC Layout

    RF IP

    RF OP

  • Simulated Performance, Example #3

    Pout at 3dB compression

    & corresponding PAE

    Small Signal S-Parameters

  • Design Example #4

    High power, X-band PA using WIN Semis 0.25m Process

    (NP25-00):

    ~ 10 to 12GHz

    25W (+44dBm) saturated output power

    >30% Efficiency

  • Choice of Device Size & PA Topology

    Start by selecting preferred device size (multiple power combined

    devices will be required)

    Recommended quiescent bias: +28V, 100mA/mm gate width

    Simulate Gmax, stabilise (if necessary) and simulate maximum

    output power (& efficiency) using a load-pull test bench

    Optimise device size until required power/efficiency is achieved, with

    sufficient gain

    Conclusion was use an 8x120um transistor cell (simulations follow)

    8 devices would then need to be combined for 25W - this is about

    the maximum practical number

  • Gmax & Stability Factor (K)

    8x120m HEMT - Device is unconditionally stable over entire X-band

    Plenty of gain

    MSG

    MAG

  • Load-pull of One Device (8x120m)

    Single device capable of delivering +36.3dBm with 45% efficiency

    8 devices should deliver +44dBm, with allowance for combiner losses

    Optimum load (at 10GHz) is 16 + j*27 Ohms

  • Schematic of 1-transistor Amplifier Cell

    Simplified ADS schematic of 1-cell:

  • Small & Large-signal Simulation of One Cell

    With matching circuit losses we achieve decent gain & close to

    the power/efficiency predicted by the load-pull test bench

    Note Output power/Efficiency presented here is at 6dB gain

    compression

  • Architecture of the 2-Stage PA

    The single-cell design is used as the basis for a driver stage

    combining 4 devices and an output stage combining 8 devices

  • Performance of Complete 2-Stage PA

    Gain > 25dB

    Positive gain slope

    Flat output power

    peak efficiency over ~ 1.5GHz bandwidth

  • Performance Summary and Layout

    Gain > 25dB (10 12GHz)

    Psat 25W (10 11.5GHz)

    PAE >33% Psat 25W (10 11.5GHz)

    DC supply at Psat: 2.75A @ +28V

    Die size: 4.8 x 4.4mm

  • Summary and Conclusions

    GaN MMIC technology is well suited to the realisation of

    microwave PAs

    A number of GaN process options are now commercially

    available

    Three Plextek RFI GaN MMIC design examples presented:

    15GHz PA for LoS links

    2-18GHz NDPA for broadband operation

    25W X-band PA for radar applications

    Dont forget to consider thermal performance

    Thanks for your time!www.plextekrfi.com

    [email protected]

    http://www.plextekrfi.com/