Bidirectional Three-Level DC-DC Converters:Sum-Difference Modeling and Control

Michael Eull and Matthias PreindlDepartment of Electrical Engineering, Columbia University in the City of New York

matthias.preindl@columbia.edu

Abstract—This paper proposes a modeling and control ap-proach for the three-level DC-DC converter. The converter isdescribed in a sum and difference (Σ∆) framework. It is shownthat the formulation is useful to model the inverter and derivedesign-specific equations. The Σ component is responsible for theinductor current, i.e. the power flow, and the ∆ component isused to balance (or unbalance) the DC-link capacitor voltages.It is shown that there are cross-coupling terms between the Σand ∆ axes that can be compensated. The proposed model isvalidated using high fidelity simulations with a proportional-integral controller. Two- and three-level converter operation isshown and it is proven that the passive components can bereduced by 50% to 75% using three-level operation withoutaffecting the control performance. The control is verified byintroducing load current and DC voltage steps.

I. INTRODUCTION

Bidirectional non-isolating DC-DC converters are a keytechnology for electrified transportation systems. They areparticularly relevant for vehicles with more-electric drivetrains[1]–[3]. DC-DC converters are used to interface energy storagesystems in electric vehicles (EV) and plug-in hybrid electricvehicles (HEV) and energy transformation units in fuel-cellvehicles [4]–[6]. The energy necessary for xEV traction can beprovided by one or more electrical energy sources or storagemediums. Non-isolating DC-DC converters are necessary tointerface different voltage levels and to control the powerflow [7], [8]. An example are EVs with hybrid energy storagesystems [9], [10], where a battery pack stores the energy fora suitable driving range and an ultracapacitor pack providespeak power and handles micro-cycling [8].

Numerous converters have been proposed and comparedin literature [7], [11]–[13]. DC-DC converters for xEV aretypically benchmarked with respect to efficiency. xEVs requirea high efficiency over a wide range of operating points thatare defined by city and highway driving cycles. A promisingsolution is the three-level DC-DC converter [14], [15] that iscapable of operating at high efficiency over wide load and highvoltage transformation ranges. In particular, this converter hasbeen shown to be highly competitive when compared to thetwo-level and two-level inverterleaved converters [16].

This paper proposes a novel modeling and control ap-proach for the three-level DC-DC converter. The converteris described in a sum and difference (Σ∆) framework. It isshown that the formulation is useful to model the inverter andderive design specific equations. Design equations are givenfor balanced operation and can be easily extended to unbal-

C1

C2

S1

S2

S3

S4

+

+

+

v1

v2

Cb vb

LiL

Ib Id

+

vd

+

vs

ic1

ic2

Fig. 1: Three-level DC-DC converter.

anced operation. The results are confirmed by simulation. Theconverter is operated in both two- and three-level operation.The latter introduces vertical interleaving to reduce passivecomponents. It is proven that the passive components can bereduced by 50% to 75% using three-level operation. The sameratio holds when comparing the 2L DC-DC (conventionalbuck-boost converter) to the 3L DC-DC converter.

The Σ∆ framework is further used for control. It canbe used in a fashion similar to the dq framework that iswidely employed in motor drives [17]. The Σ component isresponsible for current control, i.e. the power flow, whereas the∆ system is used to control the voltage sharing of the DC-link capacitors. It is shown that there are cross-coupling termsbetween the Σ and ∆ axes and that they can be compensated.Compensation is optional and can be taken care of by asufficiently fast feedback controller. The control is verified byintroducing load current and DC voltage steps in high fidelitysimulations.

II. ANALYSIS

The bidirectional three-level boost converter has four usefulswitching states. One of the upper two switches (S1 and S2)needs to be off to avoid short-circuiting the voltage v1(t).

TABLE I: Switching states, capacitor currents and outputvoltages for the three-level converter.

S1 S2 S3 S4 s(t) [ic1,ic2]′ vs(t)

off on on off [0,0]′ [0,0]′ 0on off on off [1,0]′ [−iL,0]′ v1off on off on [0,1]′ [0, − iL]

′ v2on off off on [1,1]′ [−iL, − iL]

′ v1 + v2

978-1-5090-3953-1/$31.00 ©2017 IEEE 573

Likewise, one of the lower two switches (S3 and S4) needsto be off to avoid short-circuiting the voltage v2(t). Turningboth S1 and S2 (or S3 and S4) off yields a voltage, vs(t), thatdepends on the sign of the current and is ignored in this text.The resulting useful switching states are shown in Table I andFig. 2.

To simplify the modeling, we introduce the binary switchingstate s(t) = [s1(t),s2(t)] ∈ {0,1}2 and capacitor voltagev12(t) = [v1(t),v2(t)]′ ∈ R2

+, where vd(t) = 1′v12(t) =v1(t) + v2(t) ∈ R+. Hence, the voltage that is applied tothe inductor is vs(t) = v12(t)′s(t) ∈ R+. In practice, DC-DCconverters are typically designed for Pulse Width Modulation(PWM). PWM translates a duty cycle d = [d1,d2]′ ∈ [0,1]2

into a switching sequence with time average

d =1

Tsw

∫ kTsw+Tsw

kTsw

s(t) dt, (1)

where Tsw is the switching period. Similarly, the model canbe rewritten using average modeling (neglecting second ordercomponents)

vs = v′12d = v1d1 + v2d2. (2)

Furthermore, we introduce the sum and difference notationdΣ∆ = [dΣ,d∆]′ = Td and vΣ∆ = [vΣ,v∆]′ = Tv12, where

T =

[1 11 −1

](3)

and vΣ = vd. The updated notation yields

vs =(T−1vΣ∆

)′ (T−1dΣ∆

)(4a)

=1

2v′Σ∆dΣ∆ =

1

2(vddΣ + v∆d∆) , (4b)

and the (discrete-time) dynamic equation of the inductorcurrent

i+L = iL +TsLvs −

TsLvb (5a)

= iL +Ts2L

(vddΣ + v∆d∆)− TsLvb, (5b)

where the sampling period Ts = Tsw for simplicity and .+

denotes entities of the (discrete) sampling time instant t+Ts.The voltages on capacitors C1 and C2 vary as a function ofthe inductor current and duty cycle, per

v+12 = v12 −

TsCiLd+

TsCId, (6)

where we assume C1 = C2 = C for simplicity and Id is theconstant DC current. This equation states that d1 > 0 andd2 > 0 discharges the capacitors C1 and C2 with current iL,respectively. The duty cycles d1 = 0 and d2 = 0 bypass iL anddo not affect the capacitor voltage. The equation is rewrittenusing the sum and difference notation as

v+Σ∆ = vΣ∆ −

TsCiLdΣ∆ +

[2TsCId,0

]′. (7)

(a) s = [0,0]′ (b) s = [1,0]′ (c) s = [0,1]′ (d) s = [1,1]′

Fig. 2: Conduction paths as a function of the switching states(t).

Adding the dynamic equation of the capacitor Cb, we obtainthe full dynamics of the system in scalar notation:

i+L = iL +Ts2L

(vddΣ + v∆d∆)− TsLvb, (8a)

v+∆ = v∆ −

TsCiLd∆, (8b)

v+d = vd −

TsCiLdΣ +

2TsCId, (8c)

v+b = vb +

TsCbiL −

TsCbIb; (8d)

or, in matrix form,

x+ = Ax+ B(x)u+ e, (9)

where x = [iL,v∆,vd,vb]′ is the state vector, u = dΣ∆ is theinput and e is the exogenous input. Their parameters are

A =

1 0 0 −TsL

0 1 0 00 0 1 0TsCb

0 0 1

,B(x) =

Ts2L vd

Ts2L v∆

0 −TsC iL

−TsC iL 0

0 0

, e =

00

2TsC Id

−TsCb

Ib

.The system (9) has a constant state parameter matrix and isaffine in the input with a state-dependent parameter matrix.

The state-space system (8) defines the following controlproblems that need to be addressed to operate the three-levelDC-DC converter

• Power flow: the converter transfers the power p = vbiL.Controlling the power translates into controlling iL sincevb is approximately constant (by design or control).

• Symmetric operation: Converters are typically imple-mented with one type of semiconductor and capacitor.To minimize component stresses, the capacitor voltagesshould be symmetrical, which can be achieved by con-trolling v∆ to zero.

• Voltage stabilization: Either vb or v12 can be controlledvia the power flow through the converter. The othervoltage needs to be stabilized via the exogenous input(Ib or Ic) since the converter cannot store significantamounts of energy. Stabilization can be achieved throughconnection to a DC bus or energy storage system (batteryor ultracapacitor).

574

0 10 20

pw

m

00.5

1

0 10 20

v s[V

]

0200400

0 10 20

i L[A

]

405060

0 10 20

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]

0

50

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vc

[V]

198200202

0 10 20

vd

[V]

395400405

t [us]0 10 20

v b[V

]

119.5120

120.5

(a) No interleaving, d1 = 0.3.

0 10 20

pw

m

00.5

1

0 10 20

v s[V

]

0200400

0 10 20

i L[A

]

405060

0 10 20i c

[A]

0

50

0 10 20

vc

[V]

198200202

0 10 20

vd

[V]

395400405

t [us]0 10 20

v b[V

]

119.5120

120.5

(b) Interleaving, d1 = 0.3.

0 10 20

pw

m

00.5

1

0 10 20

v s[V

]

0200400

0 10 20

i L[A

]

405060

0 10 20

i c[A

]

0

50

0 10 20

vc

[V]

198200202

0 10 20

vd

[V]

395400405

t [us]0 10 20

v b[V

]

279.5280

280.5

(c) No interleaving, d1 = 0.7.

0 10 20

pw

m

00.5

1

0 10 20

v s[V

]

0200400

0 10 20

i L[A

]

405060

0 10 20

i c[A

]

0

50

0 10 20

vc

[V]

198200202

0 10 20

vd

[V]

395400405

t [us]0 10 20

v b[V

]

279.5280

280.5

(d) Interleaving, d1 = 0.7.

Fig. 3: High fidelity simulations, with and without interleaving, for C1 = C2 = Cb = 30µF, L = 47µH and fsw = 100kHz.

0 0.2 0.4 0.6 0.8 1

i L,

v d [

pu

]

0

0.1

0.2

0.3

d1=d

2[pu]

0 0.2 0.4 0.6 0.8 10

0.01

0.02

0.03

0.04

__

v b

[pu

]_

Fig. 4: Normalized current and voltage ripples. Continuousline: analytic functions (12), (13), (15), (16), (18) and (19);markers: current (◦) and voltage (×) ripples obtained fromhigh fidelity simulation with C1 = C2 = Cb = 30µF, L =47µH and fsw = 100kHz.

III. MODULATION

The upper bridge (switches S1 and S2) is actuated bythe duty cycle d1 and the lower bridge (S3 and S4) by d2

using dedicated PWM modules. Both bridges can be operatedindependently from one another and two modulation strategiesare analyzed: two-level (2L) and three-level (3L) switching.The PWM carrier signals of the upper and lower bridge are inphase for 2L switching and phase shifted by 180◦ (Tsw/2)in 3L switching. Three-level switching can be interpretedas a vertical interleaving of the two bridges. Interleavingis generally considered to reduce current (voltage) ripples

compared to 2L switching. An example is shown in Fig.3.The switching ripples are analyzed in steady state condi-

tions. Substituting i+L = iL and v+∆ = v∆ in (28) yields vs =

vb and i∆ = 0, i.e. d∆ = 0, and d1 = d2 = dΣ/2 = vb/vd.We also assume symmetric operation, where v∆ = 0 andv1 = v2 = vd/2. This operation yields symmetric voltageand current stresses on the upper and lower bridge and it canbe shown that it yields minimum ripples. In these conditions,it can be shown that the (constant) input/output currents areIc = d1iL and Ib = iL.

Both 2L and 3L switching yield a characteristic switchingpattern in the steady state that can be observed in Fig. 3. Two-level switching only applies the switching states s(t) = [0,0]′

and s(t) = [1,1]′ such that vs(t) switches between two voltagelevels: 0V and vd. In contrast, 3L switching applies all fourswitching states and vs(t) ∈ {0V ,vd/2,vd}. Dependent on theduty cycle, vs switches between 0V and vd/2 or vd/2 and vd.In addition, 3L switching effectively doubles the switchingfrequency for the passive components.

To quantify the effects of switching, we formally definethe switching ripple as the peak-to-peak amplitude over Tswin steady state conditions. The switching ripple of inductorcurrent is defined as

iL = max iL(t)−min iL(t) ∀t ∈ [kTsw,(k + 1)Tsw], (10)

and the switching ripple of vs and vb are defined analogously.Switching ripples are calculated using the discrete versionof the characteristic inductor and capacitor equations. Theinductor current ripple results from

LiL

T= |vL|, (11)

575

where the voltage vL is assumed to be approximately constantand applied for the period T . For 2L switching, the normalizedcurrent ripple is

iL,2L(d1) =L

TswvdiL = d1(1− d1) (12)

when considering the off period where |vL| = vb = d1vd isapplied for T = (1 − d1)Tsw. With interleaving, the currentripple depends on the value of d1 as follows:

iL,3L(d1) =

{|0.5− d1|d1, if 0 ≤ d1 ≤ 0.5;|0.5− d1|(1− d1), if 0.5 < d1 ≤ 1.

(13)

For d1 ≤ 0.5 the voltage |vL| = d1vd is applied during the offinterval |0.5− d1|Tsw; for d1 ≥ 0.5, the voltage |vL| = vd −vb = (1−d1)vd is applied during the on interval |0.5−d1|Tsw.

The vd voltage ripple is computed similar to iL. Thetreatment is based on the equation

C

2

vd

T= |id|, (14)

where vd is the voltage ripple, id is the capacitor current that isassumed to be approximately constant over the period T thatit is applied, and C/2 is the resulting capacitance of the seriesconnected C1 and C2. Without interleaving, the normalizedvoltage ripple is

ˆvd,2L(d1) =C

2TswILRvd = d1(1− d1) (15)

when considering the off period where |id| = |Ib| = d1ILR isapplied for T = (1−d1)Tsw. The ripple is computed using therated (average) inductor current ILR, which yields the worst-case ripple. With interleaving, the voltage ripple is

ˆvd,3L(d1) =

{|0.5− d1|d1, if 0 ≤ d1 ≤ 0.5;|0.5− d1|(1− d1), if 0.5 < d1 ≤ 1.

(16)

For d1 ≤ 0.5 the current |ic| = |Ib| = d1ILR is applied duringthe off interval |0.5− d1|Tsw; for d1 ≤ 0.5, the current |ic| =ILR − |Ib| = (1 − d1)ILR is applied during the on interval|0.5− d1|Ts.

The computation of thevoltage ripple of vb is based on theassumption that the inductor current ripple circulates in thecapacitor. The charge, which varies with vd, is obtained byintegrating the triangular inductor current ripple in the positivehalf-period and is calculated as

Qb = Cbvb =1

2

iL2T , (17)

where T is the duration of the half-period. Without interleav-ing, we obtain the normalized voltage ripple

ˆvb,2L(d1) =LCb

T 2swvd

vb =1

8iL,2L(d1) =

1

8d1(1− d1), (18)

where T = Tsw/2. With interleaving, T = Tsw/4 and weobtain

ˆvb,3L(d1) =iL,3L(d1)

16. (19)

The normalized switching ripple is provided by (12), (13),(15), (16), (18) and (19) and shown in Fig. 4 as con-tinuous lines. The analytic equations are validated using ahigh fidelity MATLAB/Simulink model with Simscape/SPICEcomponents applying (10) to the steady state waveforms ford = 0.1,0.2, . . . ,0.9. The results are shown in Fig. 4 as markerswith current being circles (◦) and voltages crosses (×).

IV. DESIGN

The switching ripples of the presented boost converterdepend on the modulation technique. Three-level switchingsignificantly reduces the current and voltage switching ripplescompared to 2L switching. Hence, 3L switching can be usedto reduce the passive components. This section presents designequations for 2L and 3L switching.

The maximum normalized ripple is obtained by derivingthe analytic expression and setting it to zero. Using the 2Linductor current ripple as an example, we have

d

d d1

(ˆiL,2L(d1)

)= 1− 2d1 = 0 ⇔ d1,2Lmax = 0.5. (20)

In the same fashion, d1,3Lmax = 0.25 for 3L switching. Thesame duty cycles are obtained for the maximum voltageripples. The maximum 2L normalized ripples are obtained bysubstituting the duty cycles in (12), (15) and (18):

ˆiL,2Lmax = ˆvd,2Lmax = 250 · 10−3, (21a)ˆvb,2Lmax = 31.2 · 10−3. (21b)

The maximum 3L normalized ripples are obtained by sub-stituting the duty cycles in (13), (16) and (19):

ˆiL,3Lmax = ˆvd,3Lmax = 62.5× 10−3, (22a)ˆvb,3Lmax = 3.9× 10−3. (22b)

Once the maximum normalized ripples are known, the designequations result directly from (12), (15) and (18). Transform-ing these equations, we obtain

L = ˆiL,maxvd

fsw iLmax(23a)

C1 = C2 = C = ˆvd,max2ILR

fswvdmax(23b)

Cb = ˆvb,maxvd

f2swLvbmax

(23c)

where fsw = 1/Tsw is the switching frequency. The normal-ized ripples ˆiL,max, ˆvd,max and ˆvb,max are either the normalized2L switching ripples specified in (21) or the normalized 3Lswitching ripples specified in (22). The maximum peak-to-peak current ripple, iL,max is often chosen as 40% of ILR. Themaximum peak-to-peak voltage ripples vd,max and vb,max aretypically specified design requirements.

The required inductance and capacitance values can be putinto relation for a 2L and 3L design that use the same voltages(vd and vb), current (ILR), inductor current ripple (iL,max)

576

and switching frequency (fsw). The inductance L ratio andcapacitance C ratio is

L3L

L2L=

ˆiL,3Lmax

ˆiL,2Lmax

=C3L

C2L=

ˆvd,3Lmax

ˆvd2L,max=

1

4(24)

and the capacitance Cb ratio is

Cb,3L

Cb,2L=

ˆvb,3Lmax

ˆvb2L,max

ˆiL,2Lmax

ˆiL3L,max

=1

2. (25)

Hence, 2L switching requires 4 times the inductance L andcapacitance C compared to 3L switching. Although the in-ductance current ripple is the same, 3L switching requires halfthe capacitance Cb since the frequency of the current ripple is2fsw compared to just fsw for 2L switching.

The impact of the filter parameter on volume can beestimated using scaling laws [18]. The inductor volume scalesapproximately according to

YLY ∗L

=

(EL

E∗L

) 34

=

(0.5LI2

0.5L∗I2

) 34

=

(L

L∗

) 34

, (26)

where YL and EL are the inductor volume and energy,respectively. The variables with superscript .∗ belong to areference device using the same technology. The capacitorvolume scales approximately according to

YCY ∗C

=EC

E∗C=

0.5CV 2

0.5C∗V 2=

C

C∗(27)

where YC and EC are the capacitor volume and energy,respectively. Since the inductor (capacitor) works with thesame current (voltage), the volume ratio can be computedbased on the parameter values. Therefore, the inductor Lvolume can be reduced by a factor of about 2.8 using 3Lswitching compared to 2L switching. Similarly, the volume ofC and Cb can be reduced by a factor of 4 and 2, respectively.

A 2L switching-based converter is compared to a (verticallyinterleaved) 3L switching-based converter with a referencedesign for each case. The design specifications and resultsare shown in Table II.

V. CONTROL

A simple control approach is obtained by assuming that theDC voltages, vd and vb, are effectively constant with respect tosampling instants (controlled externally or due to a connectedenergy storage system). This assumption can be relaxed suchthat only one voltage is constant using a(n) (outer) voltagecontrol loop. Ignoring (8c) and (8d), the state-space model is

i+L = iL +TsLvs −

TsLvb, (28a)

v+∆ = v∆ +

TsCi∆, (28b)

where vs is used to steer iL and i∆ = −iLd∆ steers v∆. Thedynamic equations are independent from one another and can

0 10 20

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[V]

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]

199200201

(b) 3L.

Fig. 5: Reference design (Table II) validation for worst-caseduty cycles: d = 0.5 for 2L and d = 0.25 for 3L.

PIrL

iL

+-

PIrΔ

vΔ

+-

vs

iΔ

vb

++ *

÷vd/2

*÷iL

-1

dΣ

dΔ

ΣΔ

12

d1

d2

FB and FF Control Duty Cycle Calculation

.5

**vΔ/2

+-

Fig. 6: Control block diagram with feedback (FB) and feed-forward (FF) control and duty cycle calculation. The compen-sation of v∆d∆/2 (grey blocks) can be typically omitted.

be analyzed using common SISO tools, such as Bode plots.

TABLE II: Two- and three-level converter design.

Design Specification

Voltage range vd 400V . . . 800VVoltage range vb 200V . . . 400VRated current ILR 60ARipple amplitude vdmax 1%vdmin = 4VRipple amplitude vbmax 1%vbmin = 2VRipple amplitude iLmax 40%ILR = 24ASwitching frequency fsw 100kHz

Passive Design 2L 3L

Inductance L 83.3µH 20.8µHCapacitance C 75.0µF 18.8µFCapacitance Cb 15.0µF 7.5µFInductance ratio L3L/L2L 25.0%Capacitor ratio C3L/C2L 25.0%Capacitor ratio Cb3L/Cb2L 50.0%

Estimated Volume Reduction

Inductor volume ratio YL3L/YL2L 35.4%Capacitor volume ratio YC3L/YC2L 25.0%Capacitor volume ratio YCb3L/YCb2L 50.0%

577

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-]_

v S,

i Δr

[.] rL

rΔ

(a) With compensation of v∆d∆2

.

0 5 10-50

050

0 5 10-50

050

0 5 10

0

1

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d [

-]

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0.5

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0 5 10

i L[A

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50

t [ms]0 5 10

v c[V

]

180200220

d [

-]_

v S,

i Δr

[.] rL

rΔ

(b) Without compensation.

Fig. 7: Control evaluation for C1 = C2 = Cb = 30µF, L =47µH, fsw = 100kHz, with inductor current reference rL anddifference voltage reference r∆.

The discrete-time transfer functions are

tf1(z) =iLvs

=TsL

1

z − 1; tf2(z) =

v∆

i∆=TsC

1

z − 1. (29)

Power electronic systems are typically controlled usingproportional-integral (PI) feedback (FB) control thanks to itssimplicity of design and implementation. The PI controllersissue a vs and i∆ value. The integral action is used to avoidcontrol biases, for example, due to actuation uncertainties(interlock times and on-voltage drop). However, the effectof vb is large and may yield unacceptable transients, e.g. atstartup. Hence, a feedforward term is added that compensatesthe effect of vb as shown in the block diagram in Fig. 6.

The resulting control inputs vs + vb and i∆ cannot be actu-ated directly by PWM to the plant and need to be transformedinto duty cycles. In the Σ∆ framework, we have

dΣ =vs + vb − v∆d∆/2

vd/2, d∆ = − i∆

iL. (30)

The resulting scheme (with grey blocks) is shown in Fig. 6.However, the term v∆ is typically controlled to zero to ensuresymmetric operation (equivalent voltage stress and losses onC1, C2 and the switches, etc.). If v∆ ≈ 0, the effect of v∆d∆/2is small and the computation can be simplified to

dΣ =vs + vbvd/2

, d∆ = − i∆iL. (31)

Hence, the grey blocks in the block diagram in Fig. 6 cantypically be omitted. To apply the duty cycles with PWM tothe plant, dΣ∆ is transformed into d12 = T−1dΣ∆; or,

d1 =dΣ + d∆

2, d2 =

dΣ − d∆

2. (32)

It is noted that the term iL can be positive, negative orzero. If iL = 0, v∆ is constant and not controllable. Hence,the computation of d∆ in (30)–or, (31)–has to be protectedagainst division by zero. The control is shown in Fig. 7 usingsynchronous sampling.

VI. CONCLUSIONS

This paper presented a Σ∆ formulation of the three-levelDC-DC converter. Three-level operation is shown to reduceswitching ripples by 50% to 75%. Alternatively, the passivecomponents can be reduced by the same amount to achieve arequired switching ripple under the same operating conditions.The control can also be implemented in this framework andhas been demonstrated with a proportional-integral controller.

REFERENCES

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