An instant-switching D–R fractional-N frequency synthesizerwith adjustable duty cycles

Chen-Wei Huang • Ping Gui • Yanli Fan •

Mark Morgan

Received: 16 January 2011 / Revised: 5 August 2011 / Accepted: 10 August 2011 / Published online: 28 August 2011

� Springer Science+Business Media, LLC 2011

Abstract A Phase-Locked Loop (PLL)-based frequency

synthesizer (FS) with adjustable duty cycle is presented. By

employing digital processing circuitry and the D–R frac-

tional-N technique, the FS is capable of generating arbi-

trary frequencies in a wide frequency range, and capable of

adjusting the clock duty cycles. In addition, the switching

between different frequencies is instant except when a very

fine frequency resolution is required. The adjustable duty

cycle and instant switching are desired features in appli-

cations such as time-interleaved Analog-to-Digital-

Converters (ADCs), switched-capacitor circuits, and DC–

DC converters. The design was fabricated using a 0.13 lm

CMOS process. This paper gives the theories, analysis,

implementation, and measurement results of this FS.

Keywords PLL � Frequency synthesizer � D–R fractional-

N � Adjustable duty cycle � Low jitter/spurs �Instant switching

1 Introduction

As technology enters the digital era, many applications

require low-cost frequency synthesizers (FS) that are

capable of generating low-jitter arbitrary frequencies

(clocks) in a wide frequency range for multiple functional

blocks in a System-on-Chip (SoC). Instant/fast frequency

switching is another useful feature so that the operating

frequency of certain circuit blocks can be scaled for

low-power operation. In addition, in applications such as

time-interleaved analog-to-digital and digital-to-analog

converters (ADCs, DACs), it is also desirable to adjust

clock duty cycles.

Ring-VCO (voltage-controlled oscillator)-based FS is

widely used due to its capability of generating wide fre-

quency range and low cost [1, 2]. However, as the power

supply continues to scale down, the frequency range of the

VCO also shrinks, which limits their usage in practical

systems [3]. Although the VCO gain (KVCO) can be

increased to reach a wide frequency range, this increases

the clock jitters [4].

The Flying-Adder (FA) FS is capable of achieving wide

frequency range and instant switching at low cost [5–7]. In

order to meet the frequency resolution requirement, the FA

synthesizer adopts the Time-Average-Frequency (TAF)

concept [8]. However, the TAF approach introduces large

jitter/spurs whose value depends on the number of stages

and the frequency of the ring-VCO. Moreover, those large

jitter/spurs cause significant distortion for applications such

as DACs and ADCs [9].

To solve the above issues, we present an FS that adopts

D–R fractional-N technique [10, 11] instead of the TAF

approach to achieve high frequency resolution while

avoiding large jitter/spurs added to the output clock.

Moreover, digital circuitry were designed and incorporated

C.-W. Huang (&) � P. Gui

Southern Methodist University, Dallas, TX 75205, USA

e-mail: chenweih@smu.edu

P. Gui

e-mail: pgui@smu.edu

Present Address:C.-W. Huang

Integrated Device Technology, Tempe, AZ 85282, USA

Y. Fan � M. Morgan

Texas Instruments, Dallas, TX 78243, USA

123

Analog Integr Circ Sig Process (2012) 72:89–95

DOI 10.1007/s10470-011-9756-9

in the FS to adjust clock duty cycles, which are needed in

applications such as time-interleaved ADCs, switched-

capacitor circuits, and DC–DC converters [12–14]. The

concept and the preliminary simulation result of the pro-

posed technique were first introduced in [15]; the detailed

silicon implementation and measurement results of the

above FS will be demonstrated in this paper.

The paper is organized as follows. Section 2 gives a

brief introduction on the FA-FS architecture, the TAF

concept, and their drawbacks. Section 3 presents in detail

the architecture and circuitry of the proposed FS. Section 4

shows the measurement results. Finally, Sect. 5 concludes

the paper.

2 Drawbacks of the FA-FS

The FA-FS is composed of an Integer-N Phase-Locked

Loop (PLL) with a multi-stage VCO that generates multi-

ple clock signals evenly distributed in a full clock cycle.

These same-frequency-but-different-phases clock signals

are used to synthesize desired frequency based on the

control word FREQ. Figure 1 shows the architecture of the

FA-FS. The output clock is directly related to the phase

difference -D among the multiple outputs from the VCO,

which is given as,

D ¼ TVCO=N ð1Þ

where TVCO is the VCO period, and N is the number of

VCO outputs. The frequency of FA clock, fFA, is calculated

as,

fFA ¼ fVCO � N=FREQ ð2Þ

where fVCO is the VCO frequency, N is the number of VCO

outputs, and FREQ is the frequency control signal.

Since the phase difference ‘‘D’’ is fixed, to obtain a fine

frequency resolution, the FA-FS utilizes the TAF concept,

which toggles its output between two different periods,

thus the average period falls between these two periods [1]

as shown in Fig. 2.

Although the TAF approach enhances the frequency

resolution, this is done at the cost of introducing large

jitter/spurs. Figure 3 plots the histogram of the clock

periods. In this figure, VCO operates at 1 GHz and N = 8,

thus D is 125 ps. As can be observed in Fig. 3, the overall

peak-to-peak jitter is larger than 125 ps.

These large jitter/spurs in the TAF clock would affect

the performance of systems such as ADCs and DACs,

driven by such a clock. For example, the sampling clock

used in DACs plays an important role in determining the

DAC output characteristics such as signal distortion and

Signal-to-Noise ratio (SNR). It has been analyzed in [9]

that the TAF clock could introduce sampling errors at the

digital input and cause waveform distortion at the output of

the DACs. Reference [9] provides solutions to push this

large distortion out of signal band. However, this requires

either restricting the value of FREQ or increasing the

sampling frequency. Moreover, a good low-pass filter is

necessary to suppress the out-of-band noise.

3 Circuit architecture and circuitry of the proposed

frequency synthesizer

3.1 Overview

Unlike the TAF approach, our FS design relies on the

Fractional-N technique to achieve high resolution while

A SimpleVCO/PLL

CLKOUT

Register Fractional part

Adder

Control WordFREQ[j:0]

Crystal

N equaly-spaced output phases

Address

A B CA B C

Integer part

Fig. 1 The main concept of the Flying-Adder synthesizer

T1

Ideal Clock Signal

FA Signal toggles between T2 and T2+

T1 T1 T1

T2 T2 T2 T2 +

T

Fig. 2 TAF for high resolution

Fig. 3 Histogram of TAF clock (VCO @ 1 ns and N = 8)

90 Analog Integr Circ Sig Process (2012) 72:89–95

123

avoiding the large jitter/spurs introduced by using TAF

technique. Figure 4 shows the architecture of the proposed

FS which includes a ring-VCO-based D–R fractional-N

PLL and a digital processing unit to generate the output

clock, CLK1. The post processing digital unit, consisting of

adders, multiplexers, and D-Flip-Flops (DFFs), is used to

synthesize the desired clock CLK1 and adjust the duty

cycle.

3.2 Digital processing unit

According to Sect. 2, it is clear that by increasing the

number of the VCO stages, D becomes smaller, which

improves the resolution. Unfortunately, this also increases

the power consumption. Thus, in our design, a four-stage

differential VCO which provides eight clock outputs

(N = 8) was chosen for moderate power consumption and

resolution. The frequency of CLK1 using Eq. 2 becomes,

fclk1 ¼ fVCO � N=FREQ ¼ fref � Div � 8=FREQ ð3Þ

where fref is the reference frequency, Div is the feedback

divide ratio in the PLL loop, and FREQ is the frequency

control signal for the digital processing unit.

As an example, we will illustrate how to control the duty

cycle in the FS. Recall that CLK1 is generated by toggling

the DFF whenever there is a rising edge in either path 1 or

path 2 as shown in Fig. 4. The phase difference between

path 1 and path 2 is controlled by the difference of sel1 and

sel2, which is determined by signal ‘‘Dmode’’. The duty

cycle (D) is calculated as (4) and (5) for even and odd

FREQ respectively.

D ¼FREQ

2� Dmode

FREQð4Þ

D ¼FREQ�1

2� Dmode

FREQð5Þ

The duty cycle ratios with respect to FREQ and Dmode are

given in Table 1 (frequencies can be calculated by using

Eq. 2 regardless of the value of Dmode).

The duty cycle of the PLL output clock is determined by

the phase difference of the signals from the two paths.

Table 1 shows one important characteristic of this archi-

tecture: the number of available duty cycles decreases with

the frequency. Since the duty cycle is the ratio of clock

being high over the clock period, both parameters can only

change by a step of D. This explains why a longer period

(low frequency) provides more flexibility for clock duty

cycle adjustment.

The instant frequency and duty cycle switching features

are shown in Fig. 5, where CLK1 switches between

N to

1

MU

X

N equaly-spaced output phases

PFD CP LPF VCO

÷M/M+1

Crystal

…..

N to

1

MU

X

2 to

1

MU

X

ControllerFREQ

Dmode

sel1sel2

sel1

sel2

CLK1

P0

P1

P2

P3

P7

P8

Q D8

8

8

Fig. 4 Proposed FS

Table 1 Duty cycle with respect to FREQ and Dmode (N = 8)

Dmode FREQ (%)

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0 50.00 33.33 50.00 40.00 50.00 42.86 50.00 44.44 50.00 45.45 50.00 46.15 50.00 46.67 50.00

1 N/A N/A 25.00 20.00 33.33 28.57 37.50 33.33 40.00 36.36 41.67 38.46 42.86 40.00 43.75

2 N/A N/A N/A N/A 16.67� 14.29 25.00 22.22 30.00 27.27 33.33 30.77 35.71 33.33 37.50

3 N/A N/A N/A N/A N/A N/A 12.50 11.11 20.00 18.18 25.00 23.08 28.57 26.67 31.25

4 N/A N/A N/A N/A N/A N/A N/A N/A 10.00 9.09 16.67 15.38 21.43 20.00 25.00

5 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 8.33 7.69 14.29 13.33 18.75

6 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 7.14 6.67 12.50

7 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6.25

Fig. 5 Instant frequency and duty cycle switching on CLK1

Analog Integr Circ Sig Process (2012) 72:89–95 91

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frequencies without resettling the PLL. Finer resolution

requires reconfiguring the fractional-N PLL.

3.3 Charge-pump PLL and 8-phase ring-VCO

To reduce the circuit complexity, we choose the basic PLL

components that are similar to those in [16] in our imple-

mentation. The PLL has a tri-state phase detector, a charge

pump loop filter, a digitally-synthesized 6-bit multi-mod-

ulus feedback divider in the PLL loop, a 16-bit 1st-order

D–R modulator that acts as an accumulator, and a 4-stage

differential ring VCO that generates 8 output signals as

shown in Fig. 6.

4 Measurement results

The designed FS is manufactured in CMOS 0.13 lm IBM

CMRF8SF-DM technology. Figure 7 shows the layout of the

design and the micrograph of the chip. The analog part of the

chip is designed through Cadence Virtuoso environment

whereas the rest of the blocks are digitally synthesized using

Hardware Description Language (HDL) design capture,

logic synthesis and place & route. The total chip area is

1.4 mm 9 1.4 mm. The total current consumption is 22 mA

(4 mA for analog and 18 mA for digital circuitry) using

1.65 V power supply with VCO @ 350 MHz.

The jitter analysis and time-domain waveforms were

measured and captured through Tektronix TDS7404

oscilloscope.

Figure 8 shows the worst-case VCO jitter statistics and

histogram when the PLL operates under Fractional-N mode.

In this case, the PLL reference frequency is 12.8 MHz and the

divide ratio is 25.5. The VCO peak-to-peak and RMS jitters

are 55.0 and 9.0 ps respectively at 327 MHz.

For the digital processing unit, the worst-case CLK1

jitter happens when the digital processing unit takes the

outputs of the VCO under fractional mode. In this case, the

PLL reference frequency is again 12.8 MHz, the divide

ratio is 25.5, and FREQ is set to 15. As shown in Fig. 9, the

CLK1 peak-to-peak and RMS jitters are 241.7 and 27.2 ps

respectively at 174 MHz. Compared to the TAF clock with

the same VCO, which would have peak-to-peak jitter larger

than (1/327 MHz)/8 = 382 ps, this work greatly reduces

the clock jitter.

Figure 10 demonstrates the capability of adjusting the

clock duty cycle. VCO in this case operates at about

360 MHz, and FREQ and Dmode are set to 15 and 1

respectively. Using Table 1, this should yield an output

clock with 40% duty cycle. The measured duty cycle of

CLK1 in Fig. 11 is 39.82% @ 191 MHz, which is very

close to the theoretical number. Figure 11 shows another

example where FREQ = 10.

Table 2 compares this work to the other works and

also shows significant jitter improvement compared to the

FA-FS [5] that adopts the TAF approach.

Theoretically, the highest-frequency CLK1 appears

when FREQ is set to 2, which is 4 times faster than the

VCO signal.

P5

P1

P6

P2

P7

P3

P4

P8

Fig. 6 Four-stage-eight-phase differential ring-VCO

Fig. 7 The chip micrograph and the corresponding layout

92 Analog Integr Circ Sig Process (2012) 72:89–95

123

However, limited by the combinational circuit delay in

the digital processing unit, the highest clock is around

700 MHz in the experiment. Thus, future work will be on

improving the speed of the digital processing unit and

reducing the jitter added by it.

5 Conclusion

We present a new FS that adopts D–R fractional-N tech-

nique for high frequency resolution without introducing

large jitter/spurs compared to the FA-FS. In addition,

digital circuitry are designed and incorporated in the FA to

achieve instant switching and adjustable clock duty cycles.

These features make the FS suitable for applications that

require duty cycles other than 50%. The trade-off of the

proposed approach is the limited instant-switching capa-

bility compared to the FA-FS, which means if a higher

resolution is required, one has to reconfigure the D–Rfractional-N PLL to meet the resolution requirement. In

other words, unlike changing frequency in the digital

domain, this takes certain time for the PLL to relock.

Fig. 8 Worst-case VCO jitter statistics @ 327 MHzFig. 9 Worst-case CLK1 jitter statistics @ 174 MHz

Fig. 10 VCO (360 MHz) and

CLK1 (191 MHz, FREQ = 15,

Dmode = 1) waveforms

Analog Integr Circ Sig Process (2012) 72:89–95 93

123

Acknowledgment This work was supported by Semiconductor

Research Corporation Contract 1620.001.

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Fig. 11 VCO (347 MHz) and

CLK1 (276 MHz, FREQ = 10,

Dmode = 0) waveforms

Table 2 Comparison of FSs

This work ISSCC 07’ [17] JSSC 06’ [18] JSSC 00’ [5] JSSC 02’ [19] JSSC 05’ [12]

Type PLL PLL DLL PLL DLL PWCL

Technology CMOS 0.13 lm CMOS 90 nm CMOS 0.35 lm CMOS 0.6 lm CMOS 0.35 lm CMOS 0.35 lm

Supply voltage 1.65 V 1.2 V 3.3 V 3.3 V 3.3 V 3.3 V

Adjustable duty cycle Table 1 No No No No 35–70%@5%

Reference clock (MHz) 14 N/A 240–450 N/A 250 N/A

Operating frequency 135–700 MHz *2.9 GHz 120 MHz–1.8 GHz 57–130 MHz 120 MHz–1.1 GHz 1–1.27 GHz

Instant switching Yes Yes Yes Yes Yes No

Die size (mm2) 1.96 15.18 0.07 1.7 0.07 0.14

Power (mW) 36@360 MHz 1,300 86.6@1.6 GHz 150 43 150

Peak-to-Peak jitter (ps) 240@174 MHz N/A 13.2 1,132@120 MHz 7.3 20@1.25 GHz

94 Analog Integr Circ Sig Process (2012) 72:89–95

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Chen-Wei Huang received the

B.S. degree from Fu Jen Cath-

olic University, Taipei, Taiwan,

in 2004, the M.S. and PhD

degrees in electrical engineering

from Southern Methodist Uni-

versity, University Park, TX, in

2008 and 2011. He is with

Integrated Device Technology

as an Analog IC Design Engi-

neer. His research interests

include analog, digital, and

mixed-signal IC design, and

wideband and low-jitter fre-

quency synthesizer design.

Ping Gui received the B.S. and

M.S. in Electrical Engineering

from Northwestern Polytechnic

University, Xi’an, China and the

Ph.D. in Electrical and Com-

puter Engineering from Univer-

sity of Delaware. She is

currently an assistant professor

of Electrical Engineering at

Southern Methodist University,

Dallas, TX, USA. Her primary

research interests are analog and

mixed-signal IC design for var-

ious applications, including fre-

quency synthesis, high speed

data links, circuits and systems for medical applications, and circuits

for harsh environments.

Yanli Fan is a design manager

and Senior Member of Techni-

cal Staff of Texas Instruments.

She earned a MSEE from Uni-

versity of Maryland at College

Park. She was with IBM and

Hittite Microware Corporation

before she joined TI in 2002.

She has more than 15 years

experience in RF/high-speed

analog IC design. Her design

experience includes Gigabit

SerDes, Adaptive cable equal-

izer, PLL and RF/Microwave

amplifier designs. She has seven

patents issued and seven additional filed patent disclosures.

Mark Morgan earned a BSEE

from the University of Wiscon-

sin and an MSEE from Mar-

quette University. He started his

career at Delphi Automotive

Corporation before joining TI in

1997. Mark has more than

15 years experience in high-

speed analog IC design. His

design experience includes

Gigabit SerDes, adaptive cable

equalizers, PLLs, high speed

cross-point switches and CDR

retimers. He is a Distinguished

Member Technical Staff and

holds 21 patents with 10 additional filed disclosures. Currently, he is

CTO of Interface and Clock Products business unit in HPA where he

leads advanced development in circuit and process technology

development, enables emerging technologies and drives research

initiatives through SRC and TxACE activities.

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